Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/45572 )
Change subject: writeprotect.h,c: Add Winbond support (WIP) ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/flashrom/+/45572/3/writeprotect.c File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/45572/3/writeprotect.c@938 PS3, Line 938: /* : * W25Q adds an optional byte to the standard WRSR opcode. If /CS is : * de-asserted after the first byte, then it acts like a JEDEC-standard : * WRSR command. if /CS is asserted, then the next data byte is written : * into status register 2. : */ : #define W25Q_WRSR_OUTSIZE 0x03 : static int w25q_write_status_register_WREN(const struct flashctx *flash, uint8_t s1, uint8_t s2) : { : int result; : struct spi_command cmds[] = { : { : /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ : .writecnt = JEDEC_WREN_OUTSIZE, : .writearr = (const unsigned char[]){ JEDEC_WREN }, : .readcnt = 0, : .readarr = NULL, : }, { : .writecnt = W25Q_WRSR_OUTSIZE, : .writearr = (const unsigned char[]){ JEDEC_WRSR, s1, s2 }, : .readcnt = 0, : .readarr = NULL, : }, { : .writecnt = 0, : .writearr = NULL, : .readcnt = 0, : .readarr = NULL, : }}; : : result = spi_send_multicommand(flash, cmds); : if (result) { : msg_cerr("%s failed during command execution\n", : __func__); : } : : /* WRSR performs a self-timed erase before the changes take effect. */ : programmer_delay(100 * 1000); : : return result; : } need to somehow refactor 'spi25_statusreg.c:static int spi_write_status_register_flag()' to do this as well.