Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18925
to look at the new patch set (#4).
Change subject: chipset_enable: Add support for Intel Skylake ......................................................................
chipset_enable: Add support for Intel Skylake
All publicly known Skylake / Sunrise Point PCH variants share the same register interface [1..4]. Although all SPI configuration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hidden.
To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device.
This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more.
TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings.
[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995
[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996
[3] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690
[4] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691
Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber nico.huber@secunet.com --- M chipset_enable.c M programmer.h 2 files changed, 89 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/18925/4