Attention is currently required from: Nico Huber, Thomas Walker. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52310 )
Change subject: flashchips: Add Spansion/Cypress S25FL256L ......................................................................
Patch Set 4: Code-Review+1
(3 comments)
File spi.h:
https://review.coreboot.org/c/flashrom/+/52310/comment/9d1acb92_35211bdf PS4, Line 93: Block Erase 0x53 is only supported by Spansion/Cypress S25FL-L chips. I don't think it's a JEDEC standard, so I wouldn't add these macros.
File spi25.c:
https://review.coreboot.org/c/flashrom/+/52310/comment/569069f9_c3374b21 PS4, Line 491: /* This usually takes 100-4000ms, so wait in 100ms steps. */ Datasheet for S25FL064L says typical is 300 ms, and maximum is 600 ms. Datasheet for S25FL256L says typical is 190 ms, and maximum is 363 ms.
Without checking any other datasheets, I'd say the 4000 ms in the comment could be lowered to 1000 ms.
https://review.coreboot.org/c/flashrom/+/52310/comment/0aa668bc_2ec59718 PS4, Line 621: return &spi_block_erase_52; Add an entry here too?