Attention is currently required from: Nicholas Chin, ZhiYuanNJ.
Anastasia Klimchuk has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email )
Change subject: ch347_spi: Add spi clock frequency selection ......................................................................
Patch Set 11:
(2 comments)
File ch347_spi.c:
https://review.coreboot.org/c/flashrom/+/82776/comment/07382b7a_6f740b48?usp... : PS11, Line 291: speed_index = 1; Default speed_index also needs to be 2 (to index the entry 15M)
I just thought, you now have two values, `divisor` and `speed_index` which are meant to be in sync, but it's easy to get them out of sync and this can be potential bug.
Maybe you can leave `speed_index` only? with default 2.
int speed_index = 2; /* default 15M SPI */
And then below, just always use `spispeeds[speed_index].divisor`
File doc/classic_cli_manpage.rst:
https://review.coreboot.org/c/flashrom/+/82776/comment/6f90e76f_4c64de52?usp... : PS11, Line 1025: The default SPI speed is 30MHz if no value is specified. Since we are returning back to 15M, you need to update here as well
The default SPI speed is 15MHz if no value is specified (which corresponds to ``spispeed=15M``).