Attention is currently required from: Nico Huber, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin. Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#2).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register.
This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI transaction is complete before initiating newer command.
BUG=b:215255210
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 --- M ichspi.c 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/2