Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67719 )
Change subject: flashchips: Add write protect bits to W25Q64JW...M ......................................................................
flashchips: Add write protect bits to W25Q64JW...M
https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&am...
BUG=b:245996788 BRANCH=None TEST=None
Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Signed-off-by: Evan Benn evanbenn@chromium.org Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Nikolai Artemiev nartemiev@google.com --- M flashchips.c 1 file changed, 32 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Nikolai Artemiev: Looks good to me, but someone else must approve
diff --git a/flashchips.c b/flashchips.c index 6fc3a84..e8413fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18393,7 +18393,7 @@ .page_size = 256, /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -18421,6 +18421,17 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, },
{