Nikolai Artemiev has submitted this change. ( https://review.coreboot.org/c/flashrom/+/79460?usp=email )
Change subject: flashchips: Add write-protect support for GD25LQ255E ......................................................................
flashchips: Add write-protect support for GD25LQ255E
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00...
BUG=b:311336475 TEST=Verified on karis
w/o this patch: $ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad --> Failed
w/ this patch: $ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad --> Pass
This lock_top_quad test did(copied from partial_lock_test()): * Disable hardware WP so we can modify the protected range. * Then enable software WP so the range is enforced and enable hardware WP so that flashrom does not disable software WP during the operation. * Check that we cannot write to the protected region. * Check that we can write to the non protected region.
Change-Id: I1425e931433c00caceaabc6037a79099d6d5eac5 Signed-off-by: Tyler Wang tyler.wang@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/79460 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nikolai Artemiev nartemiev@google.com Reviewed-by: Hsuan-ting Chen roccochen@google.com --- M flashchips.c 1 file changed, 11 insertions(+), 1 deletion(-)
Approvals: Hsuan-ting Chen: Looks good to me, approved Nikolai Artemiev: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/flashchips.c b/flashchips.c index 8c2fecd..663b01b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6557,7 +6557,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -6593,6 +6593,16 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, },
{