Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/48104 )
Change subject: CHROMIUM: flashrom: update .tested field for EN25QH128 ......................................................................
CHROMIUM: flashrom: update .tested field for EN25QH128
update .tested field from TEST_UNTESTED to TEST_OK_PREW
BUG=b:159768722 BRANCH=none TEST=Flash Duffy bios pass on running `flashrom_tester /usr/sbin/flashrom host`
Original-Change-Id: I9467588988c2cab0987737c53ace0832144ef169 Original-Signed-off-by: Tim Chen tim-chen@quanta.corp-partner.google.com Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+... Original-Reviewed-by: Edward O'Callaghan quasisec@chromium.org Original-Commit-Queue: Edward O'Callaghan quasisec@chromium.org (cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)
Change-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165 Signed-off-by: Nikolai Artemiev nartemiev@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/flashchips.c b/flashchips.c index 4aaa8ac..d47871d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5105,7 +5105,7 @@ /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers =