Attention is currently required from: Nikolai Artemiev, Sergii Dmytruk, Stefan Reinauer.
Vasily Galkin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77531?usp=email )
Change subject: flashchips: add WP features for W25X* analogous to tested W25X20 ......................................................................
Patch Set 4:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/77531/comment/d435a9e9_c5526017 : PS3, Line 19730: .decode_range = DECODE_RANGE_SPI25,
This chip seems to have unusual ranges, does DECODE_RANGE_SPI25 decode them correctly?
I can't be 100% sure since only the W25X20 from this series was phisycally tested, but according to the doc this chip has range compatible with DECODE_RANGE_SPI25.
https://www.winbond.com/resource-files/W25X05CL_G%2008012019.pdf
It says that while it has 2 non-volatile block protection bits in status register - any non-zero value just protects entire 64KiB. Actually this logic is similar to 128KiB chips with 2 block protection bits - there is 4 possible values, but obly 3 possible states, so 0b10 and 0b11 are treated identically. And for 64KiB W25X05 all 0b10, 0b11 and 0b01 are the same.
This seems to be handled fine in https://review.coreboot.org/plugins/gitiles/flashrom/+/ebda447ad9df56dae7b94... where the encoded WP lwngth is adjusted not to be greater then chip_len.
For the clarity I added some comments to the registers declaration in patch set 4.
And a "basic" test with temporarily adjusted JEDEC_RDID in dummyflasher was perfromed:
`flashrom --wp-list` correctly reports that there is only sngle range is supported: ``` Found Winbond flash chip "W25X05" (64 kB, SPI) on dummy. === This flash part has status UNTESTED for operations: WP The test status of this chip ... ... Available protection ranges: start=0x00000000 length=0x00000000 (none) start=0x00000000 length=0x00010000 (all) ```