Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68675 )
Change subject: it87spi: Plumb max_rom_decode into it8705f_write_enable() helper ......................................................................
it87spi: Plumb max_rom_decode into it8705f_write_enable() helper
Change-Id: Iec08cb4d56a8ca62f00b0f7323b36f7d2f850e81 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M board_enable.c M include/programmer.h M internal.c M it87spi.c 4 files changed, 20 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/68675/1
diff --git a/board_enable.c b/board_enable.c index ad6e63a..fe891a4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -601,7 +601,7 @@ * Suited for all boards with ITE IT8705F. * The SIS950 Super I/O probably requires a similar flash write enable. */ -int it8705f_write_enable(uint8_t port) +int it8705f_write_enable(uint8_t port, struct decode_sizes *max_rom_decode_) { uint8_t tmp; int ret = 0; @@ -620,16 +620,16 @@ msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); if (tmp & 0x02) { /* The data sheet contradicts itself about max size. */ - max_rom_decode.parallel = 1024 * 1024; + max_rom_decode_->parallel = 1024 * 1024; msg_pinfo("IT8705F with very unusual settings.\n" "Please send the output of "flashrom -V -p internal" to flashrom@flashrom.org\n" "with "IT8705: your board name: flashrom -V" as the subject to help us finish\n" "support for your Super I/O. Thanks.\n"); ret = 1; } else if (tmp & 0x08) { - max_rom_decode.parallel = 512 * 1024; + max_rom_decode_->parallel = 512 * 1024; } else { - max_rom_decode.parallel = 256 * 1024; + max_rom_decode_->parallel = 256 * 1024; } /* Safety checks. The data sheet is unclear here: Segments 1+3 * overlap, no segment seems to cover top - 1MB to top - 512kB. @@ -673,7 +673,7 @@ ret = 1; } msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n", - max_rom_decode.parallel); + max_rom_decode_->parallel); if (ret) { msg_pinfo("Not enabling IT8705F flash write.\n"); } else { diff --git a/include/programmer.h b/include/programmer.h index dba701f..d5338d9 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -221,7 +221,7 @@ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); void probe_superio_winbond(void); -int it8705f_write_enable(uint8_t port); +int it8705f_write_enable(uint8_t port, struct decode_sizes *max_rom_decode_); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -373,7 +373,7 @@ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); -int init_superio_ite(const struct programmer_cfg *cfg); +int init_superio_ite(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_);
/* trivial wrapper to avoid cluttering internal_init() with #if */ static inline int try_mtd(const struct programmer_cfg *cfg) diff --git a/internal.c b/internal.c index d12fb1b..a4710ee 100644 --- a/internal.c +++ b/internal.c @@ -296,7 +296,7 @@ #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ - init_superio_ite(cfg); + init_superio_ite(cfg, &max_rom_decode);
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &max_rom_decode)) { msg_perr("Aborting to be safe.\n"); diff --git a/it87spi.c b/it87spi.c index a022041..a9f9a64 100644 --- a/it87spi.c +++ b/it87spi.c @@ -443,7 +443,7 @@ return register_spi_master(&spi_master_it87xx, data); }
-int init_superio_ite(const struct programmer_cfg *cfg) +int init_superio_ite(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_) { int i; int ret = 0; @@ -454,7 +454,7 @@
switch (superios[i].model) { case 0x8705: - ret |= it8705f_write_enable(superios[i].port); + ret |= it8705f_write_enable(superios[i].port, max_rom_decode_); break; case 0x8686: case 0x8716: