[flashrom-gerrit] Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Nico Huber (Code Review)]

Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Martin Roth - Personal, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 12: Code-Review-1

(3 comments)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/7d4618b6_ffea2f7a 
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
            : into below error:
            : 
            : Erasing and writing flash chip... Timeout error between offset
            : 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
            : Uh oh. Erase/write failed. Checking if anything has changed.
> Please let me know if anything we need to help for moving this CL?

What was said in the first message of the comment thread.

https://review.coreboot.org/c/flashrom/+/61854/comment/382b595c_283d6679 
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> Please let me know if anything we need to help for moving this CL?

What was said in the first message of the comment thread.

Patchset:

PS12: 
Please don't submit with a commit message that risks to repeat
the confusion of this havoc review.