Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69750 )
Change subject: ichspi: Fix number of bytes for read, write, flash id, erase operation ......................................................................
ichspi: Fix number of bytes for read, write, flash id, erase operation
This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets wrongly calculated while passing the `len` as `0` instead `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id to account the `set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block erase command.
Note: `FDBC` field still holds the wrong value (3) before any HW seq operation which will be fixed with incremental patch in this train.
BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (--wp-disable): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x300 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (--wp-disable): 0x311
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ie5de7c5bd9809d146a317df56996f7f8a85ca9a5 --- M ichspi.c 1 file changed, 49 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/50/69750/1
diff --git a/ichspi.c b/ichspi.c index 4e982f0..d2600ff 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1401,7 +1401,7 @@ } msg_pdbg("Reading Status register\n");
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; @@ -1424,7 +1424,7 @@
ich_fill_data(&value, len, ICH9_REG_FDATA0);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; @@ -1520,7 +1520,7 @@
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation, hwseq_data->addr_mask)) return -1; return 0;