Attention is currently required from: Robert Zieba, Paul Menzel, Jon Murphy, Edward O'Callaghan, Karthik Ramasubramanian. Hello build bot (Jenkins), Robert Zieba, Raul Rangel, Jon Murphy, Edward O'Callaghan, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/63422
to look at the new patch set (#3).
Change subject: sb600spi.c: Use SPI100 bit mappings ......................................................................
sb600spi.c: Use SPI100 bit mappings
On AMD SoCs that use SPI100 engine, flashrom has been using legacy spi100 register and bit mappings when programming the engine - specifically when programming the opcode and triggering their execution. --------------------------------------------------------------------- | Register Name | Legacy SPI100 mapping | Updated SPI100 mapping | |---------------|------------------------|--------------------------| | Opcode | Offset 0 from SPI BAR | Offset 0x45 from SPI BAR | | | Bits 0:7 | Bits 0:7 | |---------------|------------------------|--------------------------| | Execute Cmd | Offset 2 from SPI BAR | Offset 0x47 from SPI BAR | | | Bit 1 | Bit 7 | --------------------------------------------------------------------- These legacy register mappings are removed in upcoming generations of AMD SoCs. Stop using the legacy spi100 registers. For more details about SPI100 refer to document: 56569-A1 Rev 3.01
BUG=b:228238107 TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able to detect the SPI ROM chip, read from it and write to it successfully. Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC) successfully and ensured that all the tests passed.
Change-Id: If42130757331f4294b5a42c848557d3287f24fc3 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M sb600spi.c 1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/63422/3