Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58570 )
Change subject: spi25_statusreg,flashchips: add SR2 read/write support ......................................................................
Patch Set 23:
(3 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58570/comment/df799c75_44d020ab PS22, Line 145: #define FEATURE_RDSR2 (1 << 21)
Isn't this implied by the above and function pointers that make use of it? […]
Done
https://review.coreboot.org/c/flashrom/+/58570/comment/42480b1e_f6181556 PS22, Line 147:
Only one empty line please.
Done
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/1d81735c_f68fcef7 PS18, Line 6711: FEATURE_WRSR_EXT
Interesting, looks like the datasheet is inconsistent. It first states: […]
I tested it by writing to the QE bit in SR2 (since the SRP1 isn't writable unless you get special chips with powercycle / permanent protection modes enabled) and both commands worked.
My understanding of section 7.5 is roughly that CS# going high after 8 bits will just write SR1, and CS# going high after 16 bits will write SR1+SR2. The section you quote implies otherwise but I'd assume it was written for a different chip and just not updated for this one.