Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18883 )
Change subject: Handle Intel Wildcat Point _LP_ like Lynx Point LP ......................................................................
Handle Intel Wildcat Point _LP_ like Lynx Point LP
The subtle difference was ignored when adding these chipsets.
I'm not sure how to accound for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct.
Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber nico.huber@secunet.com --- M chipset_enable.c M ich_descriptors.c M programmer.h 3 files changed, 18 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/18883/1
diff --git a/chipset_enable.c b/chipset_enable.c index 1191a4c..c40e10f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -643,6 +643,7 @@ straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -661,6 +662,7 @@ bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: /* Lynx Point LP uses a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; @@ -796,6 +798,12 @@ static int enable_flash_pch9(struct pci_dev *dev, const char *name) { return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + +/* Wildcat Point LP */ +static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); }
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1787,13 +1795,13 @@ {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, - {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, - {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, - {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, - {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL}, {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 90f70ee..593a375 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -142,7 +142,8 @@ case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: - case CHIPSET_9_SERIES_WILDCAT_POINT: { + case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; diff --git a/programmer.h b/programmer.h index 667f6d4..52ed9a9 100644 --- a/programmer.h +++ b/programmer.h @@ -649,6 +649,7 @@ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, + CHIPSET_9_SERIES_WILDCAT_POINT_LP, };
/* ichspi.c */