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Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS4:
> Maybe glibc uses some redefines. They use both, __asm__ and asm symbols internally. […]
Hm, though a little bit unclear to me. However, I changed the commit message. I hope this is better.
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I'd like you to reexamine a change. Please visit
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Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
hwaccess: use __asm__ as it is done elsewhere
`asm()` doesn't work with musl libc. Thus, use `__asm__` as it is done
elsewhere and fix compilation under non glibc.
Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a
Signed-off-by: Rosen Penev <rosenp(a)gmail.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M hwaccess_physmap.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/63487/6
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Change subject: cli_classic.c: Make -r/-w/-v argument optional
......................................................................
cli_classic.c: Make -r/-w/-v argument optional
Makes filename optional from -r/-w/-v since the -i parameter allows
building the image to be written from multiple files, and regions to be
read from flash and written to separate image files,
Signed-off-by: Daniel Campello <campello(a)chromium.org>
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Change-Id: I15384b92cb987a6ea1bb4369ef415488b9cf7f41
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64488 )
Change subject: [RFC] dummyflasher: Wire variable size feature via opaque infra
......................................................................
Patch Set 2:
(1 comment)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/64488/comment/8cb5d49d_3c29eb50
PS1, Line 1269: rmst.spi = *s_mst;
: rmst.opaque = *o_mst;
> So... do you think it's too bad? :) I don't have another ideas at the moment :\
With the flashrom design in mind it's kind of undefined behavior. CB:50246
is not supposed to change behavior and I assume your current version
wouldn't work without that patch. Building hacks on hacks is exactly why
we need a bug tracker now.
Maybe worth to share: When Edward started to push chromium code, I said
sometimes it can save a lot of time to ignore the existing implementation,
find the requirements and implement it from scratch instead. I made exactly
that experience before when I tried to port things from chromium myself.
I think it's the same with code on our master branch today. If I wanted
to implement this, I'd probably checkout v1.2, implement what is needed
and then port it forward. The master branch was in a better state to add
new things back then.
Anyway, you already made much progress, so I think such a stunt is not
necessary. The only obstacle I see left is the usage of the spi read/
write/erase functions. So how about you try one version without them,
i.e. memcpy()/memset() instead. Hmmm, looking at emulate_spi_chip_
response(), also setting `emu_modified` in case but that seems to be
all to do. And then let the customer team test that? If it works, there
is no need to discuss hacks.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64540 )
Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 2:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/64540/comment/e7f81b2d_550acf74
PS1, Line 122: FIXME(quasisec): Port to new macros? - Control bits
> @Subrata, what did you suggest downstream to clean this up here?
I don't think you need any of these new macro here.
line #138 onwards should care of of everything.
You just need two new macro as in below:
#define HSFC_CYCLE_WR_STATUS HSFC_FCYCLE(7)
#define HSFC_CYCLE_RD_STATUS HSFC_FCYCLE(8)
and update the read/write status as https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/…
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Change subject: [RFC] dummyflasher: Wire variable size feature via opaque infra
......................................................................
Patch Set 2:
(1 comment)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/64488/comment/7e756c7d_8b7f8197
PS1, Line 1269: rmst.spi = *s_mst;
: rmst.opaque = *o_mst;
> > It's not supposed to work like this. […]
I'd suggest looking at ichspi.c function `init_ich_default()`, near the end it registers either a SPI master or an opaque master depending on the chosen mode (hardware/software sequencing).
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Change subject: [RFC] dummyflasher: Wire variable size feature via opaque infra
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64488/comment/6195146d_bdb43c4b
PS2, Line 20: TEST
A comment for myself: check with the users of "variable size" feature to make sure their stuff does not break (that's another team).
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/64488/comment/a800a727_cdc59637
PS1, Line 129: return 0;
> Seems unnecessary. […]
I removed. Although I understand this is relevant to the conversation about spi vs opaque master, so may gets changed depending on what we decide. I will return back if needed.
https://review.coreboot.org/c/flashrom/+/64488/comment/82ead7e9_82140c88
PS1, Line 133: * Once that happens, we need to have special hacks in functions:
> For opaque masters this should never happen (they all have to fill the […]
Oh yes I removed the comment. I should have done from the very beginning... I discovered that for spi infra flashctx is const and the only way the feature works is because `probe_variable_size` is linked at the very high level, directly into the chip.
I did few attempts to wire the feature via spi infra, but I couldn't because spi assumes flashctx is const.
https://review.coreboot.org/c/flashrom/+/64488/comment/8f591e84_129c56d5
PS1, Line 153: for (i = 0; i < NUM_ERASEFUNCTIONS; i++) {
> There is only one by definition (opaque entry in flashchips.c).
Thanks, I removed the loop, so now it updates that one block eraser.
https://review.coreboot.org/c/flashrom/+/64488/comment/47d853ff_55432b2d
PS1, Line 865: .read = default_spi_read,
: .write = dummy_spi_write_256,
: .erase = spi_block_erase_c7,
> It might make reasoning about the code much simpler to not re-use […]
I added dummy_opaque_read(), dummy_opaque_write(),
dummy_opaque_erase() into the struct.
However they call the same functions: default_spi_read, dummy_spi_write_256, spi_block_erase_c7. The reason is that I wanted to keep the behaviour.
But this also depends on spi vs opaque conversation.
https://review.coreboot.org/c/flashrom/+/64488/comment/8a642a7e_23b28025
PS1, Line 1269: rmst.spi = *s_mst;
: rmst.opaque = *o_mst;
> It's not supposed to work like this.
Yes I admit this is a hack! :) I thought this is an improvement from current situation because it fixes the build with CONFIG_DUMMY=no, and also now hack is contained in dummy and not splashed around the code.
I continue thinking if there is better solution, but I decided to send this patch so that we can discuss.
I also wanted to explain why this double master is needed.
First my attempt was to wire the feature as a spi master, but I couldn't make it compile: because spi infra expects flashctx to be const.
Then I started trying to wire as opaque master, as only opaque (not double). Probing was working nicely, but read/write did not work. The problem was that functions in spi.c and spi25.c they all expect `flash->mst->spi` to be present.
And I wanted to call all the same functions for read / write (the same as now). I mean right now read/write will go to dummy_spi_send_command, and I didn't want to re-write it.
This is how I got to double master. It is really an opaque master, but also it has `flash->mst->spi` available. And as the end result, dummy is using opaque chip and spi send commands.
So... do you think it's too bad? :) I don't have another ideas at the moment :\
I can see this needs to be wired as opaque master, that's for sure. But also I don't want to re-write existing dummy_spi_send_command...
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Hello build bot (Jenkins), Subrata Banik, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register()
......................................................................
spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register()
Allow specialisation in opaque masters, such as ichspi hwseq, to
write to status registers.
Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M include/programmer.h
M spi25_statusreg.c
2 files changed, 11 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Subrata Banik, Nikolai Artemiev, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
ichspi.c: Implement read_write_status for wp
The ichspi hwseq path has a opaque master specialisation that
allows for reading and writing STATUS1 registers. Hook the callbacks
with a implementation to allow for this so that writeprotect maybe
supported though this path.
Change-Id: I7ecbe8491ecea3697922c91af26ca62276e86317
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M ichspi.c
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git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/64540/2
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Change subject: [RFC] dummyflasher: Wire variable size feature via opaque infra
......................................................................
[RFC] dummyflasher: Wire variable size feature via opaque infra
Wire "variable size" feature in dummy programmer via opaque
infra. This patch fixes the broken build with CONFIG_DUMMY=no.
Dummy registers both spi and opaque structs at the same time.
The reason why this combination is needed: opaque master is needed
to reuse opaque chip and fix the building with CONFIG_DUMMY=no, at
the same time spi master is needed to reuse existing functionality
in dummy_spi_send_command.
Fixes: https://ticket.coreboot.org/issues/365
TEST=the following scenarious run successfully
Testing build
$ make clean && make CONFIG_DUMMY=no
$ flashrom -h : dummy is not in the list
$ make clean && make CONFIG_EVERYTHING=yes
$ flashrom -h : dummy is in the list
Testing "variable size" feature
$ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V
$ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V
$ head -c 8388608 </dev/urandom >/tmp/image.bin
$ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V
Testing standard flow
$ flashrom -p dummy:emulate=W25Q128FV -V
$ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V
$ head -c 16777216 </dev/urandom >/tmp/image.bin
$ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V
Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M dummyflasher.c
M flashchips.c
M include/chipdrivers.h
3 files changed, 109 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/64488/2
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58
Gerrit-Change-Number: 64488
Gerrit-PatchSet: 2
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
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Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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