Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84679?usp=email )
Change subject: doc/contact: Add note to IRC section and calm down the formatting
......................................................................
doc/contact: Add note to IRC section and calm down the formatting
Change-Id: Ic808508b5da431d6c0b88a9b2847c34c7b02cfe0
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/contact.rst
1 file changed, 12 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/84679/1
diff --git a/doc/contact.rst b/doc/contact.rst
index 79cdb91..38888fb 100644
--- a/doc/contact.rst
+++ b/doc/contact.rst
@@ -43,8 +43,8 @@
You are welcome to join and discuss current and future flashrom development, ideas and contributions.
-If you have a problem and would like to get help, don't ask for help. Instead, just **explain** your problem right away,
-and make sure to **describe** the situation as much as possible, so that other people can understand you and provide meaningful answers.
+If you have a problem and would like to get help, don't ask for help. Instead, just explain your problem right away,
+and make sure to describe the situation as much as possible, so that other people can understand you and provide meaningful answers.
Otherwise, others have to ask or guess the details of your problem, which is frustrating for both parties.
Should you need to paste lots of text (more than three lines), please use a `paste service <https://en.wikipedia.org/wiki/Pastebin>`_.
@@ -54,6 +54,12 @@
Questions on `coreboot <https://coreboot.org>`_, `OpenBIOS <http://www.openbios.info/>`_, firmware and related topics are welcome in **#coreboot** on the same server.
+Discord
+"""""""
+
+Flashrom Discord channel is hosted on coreboot's server. Once you join, you will be able to see all coreboot's and flashrom's channels in one place.
+To join, use the `invite link <https://discord.gg/dgcrkwVyeR>`_.
+
IRC
"""
@@ -68,10 +74,10 @@
with many different cultures and timezones. Most people are in the `CET timezone <https://en.wikipedia.org/wiki/Central_European_Time>`_,
so the channel may be very quiet during `CET nighttime <https://time.is/CET>`_.
-If you receive no replies, **please be patient**.
+If you receive no replies, *please be patient*.
After all, silence is better than getting replied with `"IDK" <https://en.wiktionary.org/wiki/IDK>`_.
-Frequently, somebody knows the answer, but hasn't checked IRC yet. In any case, please **do not leave the channel while waiting for an answer!**
-Since IRC does not store messages, replying to somebody who left the channel is **impossible**.
+Frequently, somebody knows the answer, but hasn't checked IRC yet. In any case, please *do not leave the channel while waiting for an answer!*
+Since IRC does not store messages, replying to somebody who left the channel is *impossible*.
To have persistence on IRC, you can set up an `IRC bouncer <https://en.wikipedia.org/wiki/Internet_Relay_Chat#Bouncer>`_
like `ZNC <https://en.wikipedia.org/wiki/ZNC>`_, or use `IRCCloud <https://www.irccloud.com/>`_.
@@ -81,11 +87,7 @@
Instead of sending lots of tiny messages with only about two words, prefer using longer sentences, spaces and punctuation symbols.
If reading and understanding your messages is easy, replying to them is also easy.
-Discord
-"""""""
-
-Flashrom Discord channel is hosted on coreboot's server. Once you join, you will be able to see all coreboot's and flashrom's channels in one place.
-To join, use the `invite link <https://discord.gg/dgcrkwVyeR>`_.
+*Note: the channel is not moderated or monitored by any of the current active maintainers.*
Dev meeting
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Anastasia Klimchuk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/flashrom/+/84102?usp=email )
Change subject: Complete and fix progress feature implementation for all operations
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Sergii, maybe you could have a look? Especially at the code which decides whether to replace previous output or print new line. I think it's the last remaining thing to do here?
I was thinking this patch can go ahead first (provided it's all good and approved), and it does not necessarily need to wait for CB:84439 ?
While I am still working on CB:84439
Thank you!
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Change subject: Display progress for what is actually erased/written
......................................................................
Patch Set 7:
(2 comments)
Patchset:
PS7:
Sergii, I forgot to add you in this patch too!
It's not fully ready yet but I am working on it. I fixed the tests and added one more test.
Also now looking into FEATURE_NO_ERASE (made a long comment about it)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/84439/comment/773f0652_6bd16650?us… :
PS7, Line 1265: // TODO: take FEATURE_NO_ERASE into account?
I found something to fix for FEATURE_NO_ERASE, although not here. This code here is fine I think, `need_erase` just compares buffers, this is fine.
However, there is another thing on FEATURE_NO_ERASE. I added a test in this patch, which runs on chip with FEATURE_NO_ERASE and progress enabled, and I can debug.
What happens is:
The emulation path calls the progress for WRITE, even though code is on the ERASE path:
Thread 1 "flashrom_unit_t" hit Breakpoint 3, progress_callback (flash=0x7fffffffc618) at ../tests/chip.c:83
83 printf("Progress almost done for stage %d\n", flash->progress_state->stage);
(gdb) p flash->progress_state->stage
$6 = FLASHROM_PROGRESS_WRITE
(gdb) bt
#0 progress_callback (flash=0x7fffffffc618) at ../tests/chip.c:83
#1 0x000055555559f2a5 in spi_write_chunked (flash=flash@entry=0x7fffffffc618, buf=buf@entry=0x7ffff2a00070 "", start=start@entry=0, len=len@entry=16777216, chunksize=256) at ../spi25.c:733
#2 0x00005555555a1293 in spi_block_erase_emulation (flash=0x7fffffffc618, addr=<optimised out>, blocklen=16777216) at ../spi95.c:69
#3 0x0000555555592cf6 in erase_write_helper (all_skipped=0x7fffffffc4af, erase_layout=0x555555e7d690, newcontents=0x7ffff4e00070 '\272' <repeats 200 times>...,
curcontents=0x7ffff3c00070 '\377' <repeats 200 times>..., region_end=16777215, region_start=0, flashrom_flashctx=0x7fffffffc618) at ../erasure_layout.c:270
#4 erase_write (flashrom_flashctx=flashrom_flashctx@entry=0x7fffffffc618, region_start=0, region_end=16777215, curcontents=curcontents@entry=0x7ffff3c00070 '\377' <repeats 200 times>...,
newcontents=newcontents@entry=0x7ffff4e00070 '\272' <repeats 200 times>..., erase_layout=0x555555e7d690, all_skipped=0x7fffffffc4af) at ../erasure_layout.c:393
#5 0x0000555555595938 in write_by_layout (all_skipped=0x7fffffffc4af, newcontents=0x7ffff4e00070, curcontents=0x7ffff3c00070, flashrom_flashctx=0x7fffffffc618) at ../flashrom.c:1470
#6 flashrom_image_write (flashrom_flashctx=flashrom_flashctx@entry=0x7fffffffc618, buffer=buffer@entry=0x7ffff4e00070, buffer_len=buffer_len@entry=16777216, refbuffer=refbuffer@entry=0x0) at ../flashrom.c:2023
#7 0x000055555558ac67 in write_chip_feature_no_erase_with_progress (state=<optimised out>) at ../tests/chip.c:605
#8 0x00007ffff7fa44e1 in ?? () from /lib/x86_64-linux-gnu/libcmocka.so.0
#9 0x00007ffff7fa4ec5 in _cmocka_run_group_tests () from /lib/x86_64-linux-gnu/libcmocka.so.0
#10 0x0000555555586170 in main (argc=<optimised out>, argv=<optimised out>) at ../tests/tests.c:512
So when no_erase chips are erased, there is `spi_write_chunked` invoked under the hood, which is updating progress for write operation (even though actual operation is erase).
By the time erase completes (it does), current progress for write is already at 100% (because it has been updated during erase). So, when writing starts, it keeps going further and increases total on the fly in libflashrom.c:95 and total eventually becomes twice more than it should.
I will look at this.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84439?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Display progress for what is actually erased/written
......................................................................
Display progress for what is actually erased/written
Change-Id: I88ac4d40f1b6ccc1636b1efb690d8d68bdebec08
Co-developed-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Co-developed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/classic_cli_manpage.rst
M flashrom.c
M tests/chip.c
M tests/tests.c
M tests/tests.h
5 files changed, 104 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/84439/7
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Anastasia Klimchuk has posted comments on this change by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84614?usp=email )
Change subject: erasure_layout: Erase larger block only when all sub-block need erase
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Bill, thank you so much for looking into the details of the erasure logic! And the patch with the test scenario, I appreciate so much!
My first thought is that this needs a test, and the fact that existing tests are passing both before and after the patch means this scenario is not really tested. It should be. I am going to inspect existing cases (in tests/erase_func_algo.c) and either add or modify something. I will post here how it goes.
As you said, this code is hardware independent, I have hopes to eventually get it fully covered with tests.
Also, very important two points that you described in commit message. I think that p.2 should be fixed regardless of p.1, because it creates the situation of redundant double erase.
I would call it "nested sub-blocks" instead of "double sub-blocks", what do you think?
p.1 is a good question to discuss. My understanding, the idea was that if we have a region, and there are many small blocks inside that need erase, maybe it's faster to send one opcode once, and erase the whole region (instead of sending lots of opcodes for each small region).
How to decide when "maybe it's faster" was a threshold of how much area is covered by small blocks. And before the patch the threshold was 50% , you changed it to 100%.
I am thinking that maybe the optimal is in between?
And anyway, I think p.2 needs to be fixed. Not in this patch. I now want to make a patch which changes the code to fix p.2 and also write a test which would fail on head but succeed on the patch. Will you give me some time for this?
Also by the way, some time ago I discovered the opposite issue (smaller blocks selected instead of larger one), which I recorded as a failing test in CB:82723. Haven't started looking into it yet, but surely I want to. Just mentioning here because it belongs to the same topic.
Oh, it's a long comment, to summarise the questions are
> And before the patch the threshold was 50% , you changed it to 100%.
I am thinking that maybe the optimal is in between?
> I now want to make a patch which changes the code to fix p.2 and also write a test which would fail on head but succeed on the patch. Will you give me some time for this?
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Change subject: ichspi: Probe opcode in POSSIBLE_OPCODES[] as well
......................................................................
Patch Set 5: Code-Review+2
(3 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/84253/comment/ca73d0b1_ef2bbd2d?us… :
PS1, Line 664: int oppos = 2; // use original JEDEC_BE_D8 offset
> I made a separate patch CB:84567 in case it end up being useful. […]
Okay I am closing this thread
https://review.coreboot.org/c/flashrom/+/84253/comment/af921339_559b1464?us… :
PS1, Line 1843:
: static bool ich_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
: {
: return find_opcode(curopcodes, opcode) >= 0;
> Please show me your elegant solution to program other erasing opcodes on the fly, but not before CB:84567 and CB:84593. ;-)
You win, you are more elegant :) I had in my mind checking inside `ich_spi_probe_opcode` for all erase opcodes, but I was thinking about hardcoded list of (JEDEC_SE, JEDEC_BE_52, JEDEC_BE_D8, JEDEC_CE_C7). You made it better by checking for POSSIBLE_OPCODES.
Can we mark this thread as resolved?
The only question that I have left, maybe you have a chance to test at the end of the chain? Thank you!
https://review.coreboot.org/c/flashrom/+/84253/comment/7c42712f_f29733d0?us… :
PS1, Line 2078: reg
> However, is it okay to just use spi_master_ich9 here? (maybe after renaming it to "spi_master_ich79" […]
Thanks for fixing! in CB:84593
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Change subject: ichspi: Merge spi_master implementations for Intel ich
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
> This looks good to me, it seems like probe_opcode was just accidentally left out of ich7.
Yes I agree, it looks like probe_opcode should be in both structs, and yes with that they can be merged.
I also did some reading of the git history, nothing there that would contradict.
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Change subject: ichspi: const-correct POSSIBLE_OPCODES[]
......................................................................
Patch Set 1: Code-Review+2
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Change subject: ichspi: Change the opcode position for reprogramming on the fly 2->4
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Oh you put my patch first in the chain, this is so nice thank you! :)
I think CB:84253 would fix the issue by itself, but I still think this patch is useful, it reduces the number of "reprogramming operations".
I also wanted to ask, maybe you can test the chain? Or maybe you did it already. Thank you!
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Change subject: ichspi: Probe opcode in POSSIBLE_OPCODES[] as well
......................................................................
Patch Set 5:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/84253/comment/7b02b334_dbc4c0c5?us… :
PS1, Line 1843:
: static bool ich_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
: {
: return find_opcode(curopcodes, opcode) >= 0;
> Merging the masters seems fine to me. […]
Oh, ignore my comment about rebasing on CB:84593, I see it's already the parent of this patch. I think I was confused by looking at an older patchset before.
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Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org>
Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com>
Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>