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[S] Change in flashrom[master]: layout: layout_next_included_region() return a region not romentry
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70892 ) Change subject: layout: layout_next_included_region() return a region not romentry ...................................................................... layout: layout_next_included_region() return a region not romentry Do exactly what it says on the tin, no need to return they wrapping ADT structure, just return the found data within the ADT. Change-Id: Ibeab87c87b9da3112e1866bc058e0f85bacddc7a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.c M include/layout.h M layout.c 3 files changed, 19 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/70892/1 diff --git a/flashrom.c b/flashrom.c index e271614..2fb532e 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1806,11 +1806,10 @@ uint8_t *const newcontents, const uint8_t *const oldcontents) { const struct flashrom_layout *const layout = get_layout(flashctx); - const struct romentry *included; + const struct flash_region *region; chipoff_t start = 0; - while ((included = layout_next_included_region(layout, start))) { - const struct flash_region *region = &included->region; + while ((region = layout_next_included_region(layout, start))) { if (region->start > start) { /* copy everything up to the start of this included region */ memcpy(newcontents + start, oldcontents + start, region->start - start); diff --git a/include/layout.h b/include/layout.h index 70d99cb..61ab9c2 100644 --- a/include/layout.h +++ b/include/layout.h @@ -66,7 +66,7 @@ int process_include_args(struct flashrom_layout *, const struct layout_include_args *); void cleanup_include_args(struct layout_include_args **); -const struct romentry *layout_next_included_region(const struct flashrom_layout *, chipoff_t); +const struct flash_region *layout_next_included_region(const struct flashrom_layout *, chipoff_t); const struct romentry *layout_next_included(const struct flashrom_layout *, const struct romentry *); const struct romentry *layout_next(const struct flashrom_layout *, const struct romentry *); int included_regions_overlap(const struct flashrom_layout *); diff --git a/layout.c b/layout.c index 6af0e41..1206b59 100644 --- a/layout.c +++ b/layout.c @@ -357,7 +357,7 @@ } } -const struct romentry *layout_next_included_region( +const struct flash_region *layout_next_included_region( const struct flashrom_layout *const l, const chipoff_t where) { const struct romentry *entry = NULL, *lowest = NULL; @@ -371,7 +371,7 @@ lowest = entry; } - return lowest; + return &lowest->region; } const struct romentry *layout_next_included( -- To view, visit https://review.coreboot.org/c/flashrom/+/70892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibeab87c87b9da3112e1866bc058e0f85bacddc7a Gerrit-Change-Number: 70892 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashrom: Check for flash access restricitons in write_flash()
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Attention is currently required from: Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70516 ) Change subject: flashrom: Check for flash access restricitons in write_flash() ...................................................................... Patch Set 5: (2 comments) File flashrom.c: https://review.coreboot.org/c/flashrom/+/70516/comment/b85c1ce4_1e2ea5ca PS5, Line 367: } ``` } free(region.name); ``` https://review.coreboot.org/c/flashrom/+/70516/comment/2ffa92db_08c08a1a PS5, Line 371: spurious -- To view, visit https://review.coreboot.org/c/flashrom/+/70516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idacf0d5218da9d9929f4877fc7665fe608b87fe0 Gerrit-Change-Number: 70516 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sat, 17 Dec 2022 00:00:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips.c: Mark W25Q128.V WP as tested
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70866 ) Change subject: flashchips.c: Mark W25Q128.V WP as tested ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/70866/comment/2ccaccd6_c13dbb96 PS1, Line 7: wp > nit: Capitalise `WP`? Done. -- To view, visit https://review.coreboot.org/c/flashrom/+/70866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Gerrit-Change-Number: 70866 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Dec 2022 23:54:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips.c: Mark W25Q128.V WP as tested
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70866 ) Change subject: flashchips.c: Mark W25Q128.V WP as tested ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/70866/comment/aefcddac_14917196 PS1, Line 9: b:? > What does it mean? :) Done -- To view, visit https://review.coreboot.org/c/flashrom/+/70866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Gerrit-Change-Number: 70866 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Dec 2022 23:54:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips.c: Mark W25Q128.V WP as tested
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Attention is currently required from: Edward O'Callaghan. Hello build bot (Jenkins), Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70866 to look at the new patch set (#3). Change subject: flashchips.c: Mark W25Q128.V WP as tested ...................................................................... flashchips.c: Mark W25Q128.V WP as tested BUG=b:258755442 TEST=`-p internal --wp-status`. Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashchips.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/70866/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/70866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Gerrit-Change-Number: 70866 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashchips.c: Mark W25Q128.V WP as tested
by Edward O'Callaghan (Code Review) 17 Dec '22

17 Dec '22

Attention is currently required from: Edward O'Callaghan. Hello build bot (Jenkins), Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70866 to look at the new patch set (#2). Change subject: flashchips.c: Mark W25Q128.V WP as tested ...................................................................... flashchips.c: Mark W25Q128.V WP as tested BUG=b:? TEST=`-p internal --wp-status`. Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashchips.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/70866/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/70866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Gerrit-Change-Number: 70866 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: chipset_enable.c: add PCI ID for TGL-UP3
by Jan Samek (Code Review) 16 Dec '22

16 Dec '22

Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70388 ) Change subject: chipset_enable.c: add PCI ID for TGL-UP3 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/70388/comment/b5d147f5_8936c8ef PS2, Line 7: SPI controller > Drop, since it's not for the SPI controller? Fair point. -- To view, visit https://review.coreboot.org/c/flashrom/+/70388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Gerrit-Change-Number: 70388 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Dec 2022 13:55:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: chipset_enable.c: add PCI ID for TGL-UP3
by Jan Samek (Code Review) 16 Dec '22

16 Dec '22

Attention is currently required from: Jan Samek. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70388 to look at the new patch set (#3). Change subject: chipset_enable.c: add PCI ID for TGL-UP3 ...................................................................... chipset_enable.c: add PCI ID for TGL-UP3 Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC. Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M chipset_enable.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/70388/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/70388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Gerrit-Change-Number: 70388 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller
by Angel Pons (Code Review) 16 Dec '22

16 Dec '22

Attention is currently required from: Jan Samek. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70388 ) Change subject: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/70388/comment/21fbbd38_0d184113 PS2, Line 7: SPI controller Drop, since it's not for the SPI controller? File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/70388/comment/6f8326bc_55c08313 PS1, Line 2083: 0xa0a4 > All operations (-r, -E, -w, -v) on TGL-UP3 proved working with 8086:0a88. Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/70388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Gerrit-Change-Number: 70388 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 16 Dec 2022 13:28:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller
by Jan Samek (Code Review) 16 Dec '22

16 Dec '22

Attention is currently required from: Angel Pons. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70388 ) Change subject: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller ...................................................................... Patch Set 2: (1 comment) File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/70388/comment/4afe29de_c155ab1f PS1, Line 2083: 0xa0a4 > Thanks for looking it up! All operations (-r, -E, -w, -v) on TGL-UP3 proved working with 8086:0a88. -- To view, visit https://review.coreboot.org/c/flashrom/+/70388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Gerrit-Change-Number: 70388 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 16 Dec 2022 11:19:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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