Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59709 )
(
31 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: spi25_statusreg.c: support reading security register
......................................................................
spi25_statusreg.c: support reading security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing special write commands
with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL
commands). No WREN is necessary, but at least some datasheets indicate
BUSY state after those write commands.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
The register is found in at least these chips by Macronix:
* MX25L6436E
* MX25L6445E
* MX25L6465E
* MX25L6473E
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M include/flash.h
M include/spi.h
M spi25_statusreg.c
3 files changed, 63 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
Edward O'Callaghan: Looks good to me, approved
Nikolai Artemiev: Looks good to me, but someone else must approve
diff --git a/include/flash.h b/include/flash.h
index ea8e25b..197c11e 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -155,6 +155,12 @@
#define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2)
#define FEATURE_WRSR3 (1 << 23)
+/*
+ * Whether chip has security register (RDSCUR/WRSCUR commands).
+ * Not to be confused with "secure registers" of OTP.
+ */
+#define FEATURE_SCUR (1 << 24)
+
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
#define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00)
@@ -189,6 +195,7 @@
STATUS1,
STATUS2,
STATUS3,
+ SECURITY,
MAX_REGISTERS
};
diff --git a/include/spi.h b/include/spi.h
index 9b38cab..c77866c 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -167,6 +167,16 @@
#define JEDEC_WRSR3_OUTSIZE 0x02
#define JEDEC_WRSR3_INSIZE 0x00
+/* Read Security Register */
+#define JEDEC_RDSCUR 0x2b
+#define JEDEC_RDSCUR_OUTSIZE 0x01
+#define JEDEC_RDSCUR_INSIZE 0x01
+
+/* Write Security Register */
+#define JEDEC_WRSCUR 0x2f
+#define JEDEC_WRSCUR_OUTSIZE 0x01
+#define JEDEC_WRSCUR_INSIZE 0x00
+
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index d0ce859..2859b23 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -100,6 +100,13 @@
}
msg_cerr("Cannot write SR3: unsupported by chip\n");
return 1;
+ case SECURITY:
+ /*
+ * Security register doesn't have a normal write operation. Instead,
+ * there are separate commands that set individual OTP bits.
+ */
+ msg_cerr("Cannot write SECURITY: unsupported by design\n");
+ return 1;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -195,6 +202,13 @@
}
msg_cerr("Cannot read SR3: unsupported by chip\n");
return 1;
+ case SECURITY:
+ if (feature_bits & FEATURE_SCUR) {
+ read_cmd = JEDEC_RDSCUR;
+ break;
+ }
+ msg_cerr("Cannot read SECURITY: unsupported by chip\n");
+ return 1;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Gerrit-Change-Number: 59709
Gerrit-PatchSet: 33
Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69781
to look at the new patch set (#6).
Change subject: util/pkgbuilds: Add musl PKGBUILDs
......................................................................
util/pkgbuilds: Add musl PKGBUILDs
WIP
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
---
A util/pkgbuilds/aarch64-linux-musl-gcc-wrapper/PKGBUILD
A util/pkgbuilds/arm-linux-musl-gcc-wrapper/PKGBUILD
A util/pkgbuilds/libusb/PKGBUILD
A util/pkgbuilds/riscv64-linux-musl-gcc-wrapper/PKGBUILD
4 files changed, 187 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/69781/6
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I28f524a53897685ab763c48f8be5370b8f6488b6
Gerrit-Change-Number: 69781
Gerrit-PatchSet: 6
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Thomas Heijligen.
Hello build bot (Jenkins), Thomas Heijligen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69714
to look at the new patch set (#6).
Change subject: flashrom/gui: Add GUI to Flashrom
......................................................................
flashrom/gui: Add GUI to Flashrom
Flashrom Graphical User Interface
Depends on:
* gtk+ >=4
* adwaita >=1
Shortcomings:
* Untested
TODO:
* Test on as many hardware/platforms as possible
Change-Id: I130028b07e0465a2c877d5cbbdc2edd9ea5e8266
Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com>
---
A gflashrom/Makefile
A gflashrom/chartable.c
A gflashrom/chartable.h
A gflashrom/common_macros.h
A gflashrom/common_ui.c
A gflashrom/common_ui.h
A gflashrom/config.h
A gflashrom/configuration.c
A gflashrom/configuration.h
A gflashrom/context_menu.ui.xml
A gflashrom/converter.c
A gflashrom/converter.h
A gflashrom/coreboot.Gflashrom.gschema.xml
A gflashrom/data_buffer.c
A gflashrom/data_buffer.h
A gflashrom/find_dialog.ui.xml
A gflashrom/find_options.ui.xml
A gflashrom/findreplace.c
A gflashrom/findreplace.h
A gflashrom/flashrom.c
A gflashrom/gflashrom.c
A gflashrom/gflashrom.css
A gflashrom/gflashrom.gresource.xml
A gflashrom/gflashrom.h
A gflashrom/gflashrom_app_win.c
A gflashrom/gflashrom_app_win.h
A gflashrom/gflashrom_app_win.ui.xml
A gflashrom/gflashrom_layout_manager.c
A gflashrom/gflashrom_layout_manager.h
A gflashrom/gflashrom_paste_data.c
A gflashrom/gflashrom_paste_data.h
A gflashrom/gflashrom_resources.c
A gflashrom/help_overlay.ui.xml
A gflashrom/hex_dialog.c
A gflashrom/hex_dialog.h
A gflashrom/hex_document.c
A gflashrom/hex_document.h
A gflashrom/hex_statusbar.c
A gflashrom/hex_statusbar.h
A gflashrom/jump_dialog.ui.xml
A gflashrom/main.c
A gflashrom/objects.c
A gflashrom/objects.h
A gflashrom/paste_special.c
A gflashrom/paste_special.h
A gflashrom/paste_special.ui.xml
A gflashrom/preferences.c
A gflashrom/preferences.h
A gflashrom/preferences.ui.xml
A gflashrom/print.c
A gflashrom/print.h
A gflashrom/replace_dialog.ui.xml
52 files changed, 17,022 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/69714/6
--
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Gerrit-Change-Id: I130028b07e0465a2c877d5cbbdc2edd9ea5e8266
Gerrit-Change-Number: 69714
Gerrit-PatchSet: 6
Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
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Attention is currently required from: Nikolai Artemiev, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk.
Hello build bot (Jenkins), Nikolai Artemiev, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69788
to look at the new patch set (#2).
Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
Additionally, dropped unused variable (struct hwseq_data *hwseq_data).
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
---
M ichspi.c
1 file changed, 59 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/69788/2
--
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