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[S] Change in flashrom[master]: flashrom_tester: partial_lock: Use WriteProtectState cache
by Evan Benn (Code Review) 10 Nov '22

10 Nov '22

Evan Benn has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69418 ) Change subject: flashrom_tester: partial_lock: Use WriteProtectState cache ...................................................................... flashrom_tester: partial_lock: Use WriteProtectState cache partial_lock test was bypassing the WriteProtectState cache of the software write protect by directly calling env.cmd.wp_range. It was also unnesesarily disabling software WP. Fix those issues and more clearly document what the test is doing and expecting. BUG=b:244663741 BRANCH=None TEST=flashrom_tester --libflashrom host Change-Id: Ic3f89ff5d22e74e4e6c94e755b936e58cb27182d Signed-off-by: Evan Benn <evanbenn(a)chromium.org> --- M util/flashrom_tester/src/tester.rs M util/flashrom_tester/src/tests.rs 2 files changed, 43 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/69418/1 diff --git a/util/flashrom_tester/src/tester.rs b/util/flashrom_tester/src/tester.rs index a97204d..3485a50 100644 --- a/util/flashrom_tester/src/tester.rs +++ b/util/flashrom_tester/src/tester.rs @@ -244,6 +244,24 @@ } } + // Set software write protect with a custom range + pub fn set_range(&mut self, range: (i64, i64), enable: bool) -> Result<&mut Self, String> { + info!("set_range request={}, current={}", enable, self.current.sw); + self.cmd + .wp_range(range, enable) + .map_err(|e| e.to_string())?; + let actual_state = Self::get_sw(self.cmd).map_err(|e| e.to_string())?; + if actual_state != enable { + Err(format!( + "set_range request={}, real={}", + enable, actual_state + )) + } else { + self.current.sw = enable; + Ok(self) + } + } + /// Set the hardware write protect if supported and check that the state is as expected. pub fn set_hw(&mut self, enable: bool) -> Result<&mut Self, String> { info!("set_hw request={}, current={}", enable, self.current.hw); diff --git a/util/flashrom_tester/src/tests.rs b/util/flashrom_tester/src/tests.rs index 60f1c6e..996ce0e 100644 --- a/util/flashrom_tester/src/tests.rs +++ b/util/flashrom_tester/src/tests.rs @@ -271,10 +271,12 @@ env.ensure_golden()?; let (wp_section_name, start, len) = utils::layout_section(env.layout(), section); - // Disable software WP so we can do range protection, but hardware WP - // must remain enabled for (most) range protection to do anything. - env.wp.set_hw(false)?.set_sw(false)?; - env.cmd.wp_range((start, len), true)?; + // Disable hardware WP so we can modify the protected range. + env.wp.set_hw(false)?; + // Then enable software WP so the range is enforced and enable hardware + // WP so that flashrom does not disable software WP during the + // operation. + env.wp.set_range((start, len), true)?; env.wp.set_hw(true)?; // Check that we cannot write to the protected region. -- To view, visit https://review.coreboot.org/c/flashrom/+/69418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic3f89ff5d22e74e4e6c94e755b936e58cb27182d Gerrit-Change-Number: 69418 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashrom_tester: Change the wp_toggle semantics
by Evan Benn (Code Review) 10 Nov '22

10 Nov '22

Evan Benn has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69417 ) Change subject: flashrom_tester: Change the wp_toggle semantics ...................................................................... flashrom_tester: Change the wp_toggle semantics wp_toggle and wp_range had some confusing behaviour where enabling wp would set a range, but disabling wp would not unset the range (explicitly). This was a way to workaround the MTD kernel driver semantics. Now make things very explicit, enabling software write protect will set the range to the whole chip. Disabling write protect will set the range to 0,0. This makes all drivers behave the same as MTD, and documents the exact behaviour explicitly. BUG=b:244663741 BRANCH=None TEST=flashrom_tester --libflashrom host # MTD and non-MTD TEST=flashrom_tester --flashrom_binary # MTD and non-MTD Change-Id: Ia01d612d988e6580a7c5f0fd448ccc319ce9b181 Signed-off-by: Evan Benn <evanbenn(a)chromium.org> --- M util/flashrom_tester/flashrom/src/cmd.rs M util/flashrom_tester/flashrom/src/flashromlib.rs M util/flashrom_tester/flashrom/src/lib.rs 3 files changed, 34 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/69417/1 diff --git a/util/flashrom_tester/flashrom/src/cmd.rs b/util/flashrom_tester/flashrom/src/cmd.rs index 4078910..458f054 100644 --- a/util/flashrom_tester/flashrom/src/cmd.rs +++ b/util/flashrom_tester/flashrom/src/cmd.rs @@ -149,11 +149,12 @@ Ok(true) } - fn wp_range(&self, range: (i64, i64), wp_enable: bool) -> Result<bool, FlashromError> { + fn wp_range(&self, range: (i64, i64), en: bool) -> Result<bool, FlashromError> { let opts = FlashromOpt { wp_opt: WPOpt { + enable: en, + disable: !en, range: Some(range), - enable: wp_enable, ..Default::default() }, ..Default::default() @@ -200,28 +201,14 @@ } fn wp_toggle(&self, en: bool) -> Result<bool, FlashromError> { - let status = if en { "en" } else { "dis" }; - - // For MTD, --wp-range and --wp-enable must be used simultaneously. let range = if en { let rom_sz: i64 = self.get_size()?; - Some((0, rom_sz)) // (start, len) + (0, rom_sz) // (start, len) } else { - None + (0, 0) }; - - let opts = FlashromOpt { - wp_opt: WPOpt { - range, - enable: en, - disable: !en, - ..Default::default() - }, - ..Default::default() - }; - - self.dispatch(opts, "wp_toggle")?; - + self.wp_range(range, en)?; + let status = if en { "en" } else { "dis" }; match self.wp_status(true) { Ok(_ret) => { info!("Successfully {}abled write-protect", status); diff --git a/util/flashrom_tester/flashrom/src/flashromlib.rs b/util/flashrom_tester/flashrom/src/flashromlib.rs index 3036394..c948564 100644 --- a/util/flashrom_tester/flashrom/src/flashromlib.rs +++ b/util/flashrom_tester/flashrom/src/flashromlib.rs @@ -102,9 +102,6 @@ } fn wp_toggle(&self, en: bool) -> Result<bool, FlashromError> { - // TODO why does the cmd impl not do this? - // for cmd, range is only set for enable - // and disable is not sent for the wp_range command self.wp_range((0, self.get_size()?), en) } diff --git a/util/flashrom_tester/flashrom/src/lib.rs b/util/flashrom_tester/flashrom/src/lib.rs index 11874f9..f84dea5 100644 --- a/util/flashrom_tester/flashrom/src/lib.rs +++ b/util/flashrom_tester/flashrom/src/lib.rs @@ -133,7 +133,7 @@ /// Write only a region of the flash. fn write_file_with_layout(&self, rws: &ROMWriteSpecifics) -> Result<bool, FlashromError>; - /// Set write protect status for a range. + /// Set write protect status and range. fn wp_range(&self, range: (i64, i64), wp_enable: bool) -> Result<bool, FlashromError>; /// Read the write protect regions for the flash. @@ -143,6 +143,9 @@ fn wp_status(&self, en: bool) -> Result<bool, FlashromError>; /// Set write protect status. + /// If en=true sets wp_range to the whole chip (0,getsize()). + /// If en=false sets wp_range to (0,0). + /// This is the only supported behaviour from MTD fn wp_toggle(&self, en: bool) -> Result<bool, FlashromError>; /// Read the whole flash to the file specified by `path`. -- To view, visit https://review.coreboot.org/c/flashrom/+/69417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia01d612d988e6580a7c5f0fd448ccc319ce9b181 Gerrit-Change-Number: 69417 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: flashchips: Add write protect bits to W25Q64JW...M
by Edward O'Callaghan (Code Review) 10 Nov '22

10 Nov '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67719 ) Change subject: flashchips: Add write protect bits to W25Q64JW...M ...................................................................... flashchips: Add write protect bits to W25Q64JW...M https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&D… BUG=b:245996788 BRANCH=None TEST=None Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Signed-off-by: Evan Benn <evanbenn(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c 1 file changed, 32 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Nikolai Artemiev: Looks good to me, but someone else must approve diff --git a/flashchips.c b/flashchips.c index 6fc3a84..e8413fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18393,7 +18393,7 @@ .page_size = 256, /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -18421,6 +18421,17 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/67719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Gerrit-Change-Number: 67719 Gerrit-PatchSet: 5 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: flashchips: Add write protect bits to W25Q64JW...M
by Nikolai Artemiev (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Evan Benn. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67719 ) Change subject: flashchips: Add write protect bits to W25Q64JW...M ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/67719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Gerrit-Change-Number: 67719 Gerrit-PatchSet: 4 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evan Benn <evanbenn(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 04:33:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom_tester: Check the WP state when setting
by Evan Benn (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Peter Marheine. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69402 ) Change subject: flashrom_tester: Check the WP state when setting ...................................................................... Patch Set 4: (1 comment) File util/flashrom_tester/src/tester.rs: https://review.coreboot.org/c/flashrom/+/69402/comment/e09d18f8_01f80184 PS4, Line 238: let actual_state = Self::get_sw(self.cmd).map_err(|e| e.to_string())?; Aha I have discovered a bug with this. The `cmd` also has `wp_range` function, which is a bit strange and maybe enables wp but doesnt disable wp? anyway it bypasses the stored state here. -- To view, visit https://review.coreboot.org/c/flashrom/+/69402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie7f90ab478dca6f92eaa0908443e3cb156ea0319 Gerrit-Change-Number: 69402 Gerrit-PatchSet: 4 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 03:39:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: ichspi: clear byte count in ich_start_hwseq_xfer()
by Nikolai Artemiev (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69422 to look at the new patch set (#2). Change subject: ichspi: clear byte count in ich_start_hwseq_xfer() ...................................................................... ichspi: clear byte count in ich_start_hwseq_xfer() This fixes a regression introduced by a ichspi driver refactor in `commit 7ed1337309d3fe74f5af09520970f0f1d417399a` When preparing for a hwseq transfer in ich_start_hwseq_xfer(), clear the HSFC_FDBC bits before setting the new byte count. Otherwise the old byte count bits remain set, resulting in too many bytes being transferred. In particular this causes status register read/write operations to fail, and probably causes issues in other hwseq operations as well. BUG=b:257845782,b:258280679 BRANCH=none TEST=flashrom {--wp-enable,--wp-disable} Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/69422/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf Gerrit-Change-Number: 69422 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: ichspi: clear byte count in ich_start_hwseq_xfer()
by Edward O'Callaghan (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69422 ) Change subject: ichspi: clear byte count in ich_start_hwseq_xfer() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf Gerrit-Change-Number: 69422 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:42:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: ichspi: clear byte count in ich_start_hwseq_xfer()
by Nikolai Artemiev (Code Review) 10 Nov '22

10 Nov '22

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69422 ) Change subject: ichspi: clear byte count in ich_start_hwseq_xfer() ...................................................................... ichspi: clear byte count in ich_start_hwseq_xfer() When preparing for a hwseq transfer in ich_start_hwseq_xfer(), clear the HSFC_FDBC bits before setting the new byte count. Otherwise the old byte count bits remain set, resulting in too many bytes being transferred. In particular this causes status register read/write operations to fail, and probably causes issues in other hwseq operations as well. BUG=b:257845782,b:258280679 BRANCH=none TEST=flashrom {--wp-enable,--wp-disable} Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/69422/1 diff --git a/ichspi.c b/ichspi.c index 4e982f0..1c3fad3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1362,6 +1362,7 @@ hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */ hsfc |= hsfc_cycle; + hsfc &= ~HSFC_FDBC; /* clear byte count */ hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ prettyprint_ich9_reg_hsfc(hsfc, ich_generation); -- To view, visit https://review.coreboot.org/c/flashrom/+/69422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2535bdfb77ff370bddcb507a229bbf4119681cdf Gerrit-Change-Number: 69422 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: flashrom_tester: Log some cros lsb-release information
by Evan Benn (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Edward O'Callaghan, Peter Marheine. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69403 ) Change subject: flashrom_tester: Log some cros lsb-release information ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/69403/comment/89373c23_351cb4e2 PS3, Line 16: > ditto Done File util/flashrom_tester/src/tests.rs: https://review.coreboot.org/c/flashrom/+/69403/comment/da203b68_fe5010ae PS3, Line 137: CROS > 'Distro' ? do you want this to read 'Unknown CROS Distro'? -- To view, visit https://review.coreboot.org/c/flashrom/+/69403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If3452ead9e02e0ddeaa0fdf4852d7c17a8ab7650 Gerrit-Change-Number: 69403 Gerrit-PatchSet: 4 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:22:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashrom_tester: Only print color when stdout isatty
by Evan Benn (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Edward O'Callaghan. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69270 ) Change subject: flashrom_tester: Only print color when stdout isatty ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/69270/comment/60c0e6a0_568dfaf9 PS1, Line 18: > upstream needs a sign-off line Done -- To view, visit https://review.coreboot.org/c/flashrom/+/69270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia3cc527fb98e53eda6773622340cf10764df2cba Gerrit-Change-Number: 69270 Gerrit-PatchSet: 2 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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