Arnaud Ferraris has posted comments on this change by Arnaud Ferraris. ( https://review.coreboot.org/c/flashrom/+/84856?usp=email )
Change subject: linux_mtd: fix build with clang >= 19
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Arnaud, thank you for the patch! […]
Hi Anastasia,
Yes, I did run the tests, which built successfully and passed using both clang 19 and HEAD from Oct 8th.
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Matti Finder has posted comments on this change by Matti Finder. ( https://review.coreboot.org/c/flashrom/+/84840?usp=email )
Change subject: cli_classic: Add rpmc command support
......................................................................
Patch Set 4:
(1 comment)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/84840/comment/f2831dbf_d12a4008?us… :
PS3, Line 165: ", the RPMC commands"
> "a RPMC command" since specifying more than one in a single invocation is an error.
Done
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Hello Anastasia Klimchuk, Peter Marheine, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84840?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: cli_classic: Add rpmc command support
......................................................................
cli_classic: Add rpmc command support
Added optional support for all the commands specified in JESD260.
Added a new optional dependency to openssls libcrypto.
Added parsing for the rpmc parameter sfdp table.
Added necessary rpmc parameter information to flashchips struct and the
flash hardening feature to enable rpmc commands.
Tested on the Winbond W25R128JV as a 'SFDP-capable chip'.
This patch was done to add rpmc command support to flashrom.
This enables users to write root keys to their flash chips while they
flash data on the chip. This might become usefull in the future as rpmc
support is extended in coreboot.
Also adds usefull debug tools to flashrom, which might be usefull in
implementing coreboots rpmc support.
Change-Id: I36c823bbee65f256eb6edabe6f058321c9a0cfa1
Signed-off-by: Matti Finder <matti.finder(a)gmail.com>
---
M cli_classic.c
M include/flash.h
A include/rpmc.h
M meson.build
M meson_options.txt
A rpmc.c
M sfdp.c
7 files changed, 799 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/84840/4
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Anastasia Klimchuk has posted comments on this change by Alexandru Stan. ( https://review.coreboot.org/c/flashrom/+/84752?usp=email )
Change subject: flashchips: add Winbond W25R512NW / W74M51NW
......................................................................
Patch Set 2:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/84752/comment/ed44d148_c03d2437?us… :
PS2, Line 20239: 1024B total, 256B reserved
> Maybe the better comment is what's in the datasheet: […]
I have something! Another developer kindly explained to me about OTP (in another patch CB:84827), and I think we need to go by what datasheet says:
`OTP: 3X256B`
"Reserved" OTP is not mentioned in datasheet, so let's drop that part.
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Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84827?usp=email )
Change subject: flashchips: add GD25F128F
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/84827/comment/2bf40960_c9e0d3a9?us… :
PS1, Line 8199: OTP: 1024B total, 256B reserved
> Thanks. I need to make a correction here. It is 3x2048 bytes. Each can be erased and be programed.
I see that you updated, so I mark it as resolved, right?
I don't have any other comments.
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Anastasia Klimchuk has posted comments on this change by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84721?usp=email )
Change subject: erasure_layout: Add an option to sacrifice unchanged blocks for speed
......................................................................
Patch Set 10:
(1 comment)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/84721/comment/761482e9_716df6de?us… :
PS8, Line 124: " --sacrifice-ratio <ratio> Maximum %% memory that is allowed for redundant\n"
> And just right now, I realised manpage needs to be updated too! […]
So, I did all three things:
1) cli_classic.c , I combined the text from everyone! tell me what do you think
flashrom -h shows it, all good
2) doc/release_notes/devel.rst has the section, text copied from commit message
3) doc/classic_cli_manpage.rst also has the text, a bit longer than 1)
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Attention is currently required from: Aarya, Bill XIE, Peter Marheine.
Anastasia Klimchuk has uploaded a new patch set (#10) to the change originally created by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84721?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: erasure_layout: Add an option to sacrifice unchanged blocks for speed
......................................................................
erasure_layout: Add an option to sacrifice unchanged blocks for speed
The patch adds command line option to handle the following situation:
There is a region which is requested to be erased (or written, because
the write operation uses erase too). Some of the areas inside this
region don't need to be erased, because the bytes already have expected
value. Such areas can be skipped.
The logic selects eraseblocks that can cover the areas which need to be
erased. Suppose there is a region which is partially covered by
eraseblocks of size S (partially because remaining areas don't need to
be erased). Now suppose we can cover the whole region with eraseblock
of larger size, S+1, and erase it all at once. This will run faster:
erase opcode will only be sent once instead of many smaller opcodes.
However, this will run erase over some areas of the chip memory that
didn't need to be erased. Which means, the chip, as a hardware, will
wear faster.
New command line option sets the maximum % memory that is allowed for
redundant erase. Default is 0, S+1 size block only selected if all the
area needs to be erased in full. 50 means that if more than a half of
the area needs to be erased, a S+1 size block can be selected to cover
all area with one block.
The tradeoff is the speed of programming operation VS the longevity of
the chip. Default is longevity.
Change-Id: I154e8a713f626c37dbbe118db700055b96d24803
Co-developed-by: persmule <persmule(a)hardenedlinux.org
Co-developed-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Signed-off-by: persmule <persmule(a)hardenedlinux.org>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M cli_classic.c
M doc/classic_cli_manpage.rst
M doc/release_notes/devel.rst
M erasure_layout.c
M include/flash.h
M tests/erase_func_algo.c
6 files changed, 152 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/84721/10
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Anastasia Klimchuk has posted comments on this change by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84721?usp=email )
Change subject: erasure_layout: Add an option to sacrifice unchanged blocks for speed
......................................................................
Patch Set 9:
(3 comments)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/84721/comment/1f7af8a1_255511d3?us… :
PS8, Line 124: " --sacrifice-ratio <ratio> Maximum %% memory that is allowed for redundant\n"
> This is understandable, but reads somewhat awkwardly to me. Perhaps: […]
And just right now, I realised manpage needs to be updated too!
Also would be good to add info into release_notes/devel.html. I actually think to copy the long commit message that I wrote :) It can go as is (only without "this patch adds")
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/84721/comment/514f3879_91d95a7f?us… :
PS8, Line 253: needless
> needing?
That was actually the blocks that not needed to be erased, which was "needless".
I did a modification to that comment text, to say directly that's `not needed to change`
File tests/erase_func_algo.c:
https://review.coreboot.org/c/flashrom/+/84721/comment/4ee3e2e4_2e22d703?us… :
PS8, Line 1235: }
: },
: sizeof(*all_cases)
: );
: memcpy(
: &all_cases[num_parameterized * 2 + 1],
: (const struct CMUnitTest[]){
: (const struct CMUnitTest) {
: .name = "write with sacrifice ratio 50",
: .test_func = test_write_with_sacrifice_ratio50,
: }
: },
: sizeof(*all_cases)
: );
> The previous `memcpy` is already set up to copy an array of structs, so you can inline the new struc […]
Done
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Attention is currently required from: Aarya, Anastasia Klimchuk, Bill XIE.
Anastasia Klimchuk has uploaded a new patch set (#9) to the change originally created by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84721?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: erasure_layout: Add an option to sacrifice unchanged blocks for speed
......................................................................
erasure_layout: Add an option to sacrifice unchanged blocks for speed
The patch adds command line option to handle the following situation:
There is a region which is requested to be erased (or written, because
the write operation uses erase too). Some of the areas inside this
region don't need to be erased, because the bytes already have expected
value. Such areas can be skipped.
The logic selects eraseblocks that can cover the areas which need to be
erased. Suppose there is a region which is partially covered by
eraseblocks of size S (partially because remaining areas don't need to
be erased). Now suppose we can cover the whole region with eraseblock
of larger size, S+1, and erase it all at once. This will run faster:
erase opcode will only be sent once instead of many smaller opcodes.
However, this will run erase over some areas of the chip memory that
didn't need to be erased. Which means, the chip, as a hardware, will
wear faster.
New command line option sets the maximum % memory that is allowed for
redundant erase. Default is 0, S+1 size block only selected if all the
area needs to be erased in full. 50 means that if more than a half of
the area needs to be erased, a S+1 size block can be selected to cover
all area with one block.
The tradeoff is the speed of programming operation VS the longevity of
the chip. Default is longevity.
Change-Id: I154e8a713f626c37dbbe118db700055b96d24803
Co-developed-by: persmule <persmule(a)hardenedlinux.org
Co-developed-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Signed-off-by: persmule <persmule(a)hardenedlinux.org>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M cli_classic.c
M erasure_layout.c
M include/flash.h
M tests/erase_func_algo.c
4 files changed, 113 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/84721/9
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Nikolai Artemiev has posted comments on this change by Arnaud Ferraris. ( https://review.coreboot.org/c/flashrom/+/84856?usp=email )
Change subject: linux_mtd: fix build with clang >= 19
......................................................................
Patch Set 1: Code-Review+2
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