Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72056 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: Add missing Intel B460 flash chip id
......................................................................
Add missing Intel B460 flash chip id
Note that while I can read the chip, on my Lenovo Legion T5 28IMB05,
cannot write to the flash chip with any tools except upgrading with
vendor tool, no downgrades are allowed, due to the fact of SMM, even if
I did manage to flash the BIOS chip somehow, would still face bootguard
since this machine has bootguard. But if I read the chip, and verify my
read bin file, it works fine, until changing the SMBIOS, which is in
the vendor BIOS update package.
Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca
Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/72056
Reviewed-by: Thomas Heijligen <src(a)posteo.de>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M chipset_enable.c
1 file changed, 23 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Thomas Heijligen: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c
index 480113a..e1dd6a3 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2152,6 +2152,7 @@
{0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
{0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300},
{0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300},
+ {0x8086, 0xa3c8, B_S, OK, "Intel", "B460", enable_flash_pch400},
{0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch400},
{0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch400},
{0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch400},
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73037 )
Change subject: asm106x: add programmer for ASM106x SATA controllers
......................................................................
Patch Set 6: Code-Review+2
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Change subject: asm106x: add programmer for ASM106x SATA controllers
......................................................................
Patch Set 6: Verified+1
(1 comment)
Patchset:
PS6:
Tested successfully. Read write and erase with a puya spi flash found as "SFDP-capable". Same PCI-Id chip number combo as in the commit message.
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 )
Change subject: Add support for VIA VL805 USB Controller flashing
......................................................................
Patch Set 19: Verified+1
(3 comments)
Patchset:
PS19:
Tested successfully on the VIA Labs Inc. VIA VL805-QFN68 VL0127A reference card.
Read write and erase successfully on an MACRONIX MX25L1006E, recognized as "SFDP-capable chip" by flashrom
File vl805.c:
https://review.coreboot.org/c/flashrom/+/72057/comment/ee5f6706_b7c811fd
PS19, Line 120: 64 * 1024, /* Maximum data read size in one go (excluding opcode+address). */
This can be `MAX_DATA_READ_UNLIMITED`
https://review.coreboot.org/c/flashrom/+/72057/comment/698b01a2_f777a5f5
PS19, Line 121: 256, /* Maximum data write size in one go (excluding opcode+address). */
This can be `MAX_DATA_WRITE_UNLIMITED`
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Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 )
Change subject: Add support for VIA VL805 USB Controller flashing
......................................................................
Patch Set 19:
(2 comments)
File vl805.c:
https://review.coreboot.org/c/flashrom/+/72057/comment/101f1f99_4fcc96a4
PS19, Line 72: unsigned int curreadcnt;
Delete, similar to what you did for curwritecnt before
https://review.coreboot.org/c/flashrom/+/72057/comment/a16670b1_8d7591ed
PS19, Line 91: curreadcnt = min(4, readcnt - j);
Change to `uint32_t unsigned int curreadcnt;`, similar to what you did for `curwritecnt` above
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Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/72057
to look at the new patch set (#19).
Change subject: Add support for VIA VL805 USB Controller flashing
......................................................................
Add support for VIA VL805 USB Controller flashing
It works fine for me on my Raspberry Pi 4 Model B. Was able read read,
erase, write, verify. Only thing is the WP with the W25X10 gives a
untested warning.
Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38
Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com>
---
M Makefile
M flashrom.8.tmpl
M include/programmer.h
M meson.build
M meson_options.txt
M programmer_table.c
A vl805.c
7 files changed, 215 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/72057/19
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69847 )
Change subject: writeprotect: Add function to get register values and WP bit masks
......................................................................
Patch Set 9: Code-Review+1
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Change subject: asm106x: add programmer for ASM106x SATA controllers
......................................................................
Patch Set 5:
(4 comments)
File asm106x.c:
https://review.coreboot.org/c/flashrom/+/73037/comment/28979ba0_6e8ab1dc
PS5, Line 47: x
> Please use `inttype.h` macros here for fixed length integer. […]
Done
https://review.coreboot.org/c/flashrom/+/73037/comment/e57001dd_67fb5358
PS5, Line 57: msg_pdbg("asm106x timed out, ctrl 0x%02x\n", val);
> Same here `... […]
Done
https://review.coreboot.org/c/flashrom/+/73037/comment/8cb52f6a_f79995ab
PS5, Line 81: msg_pdbg2("asm106x write 0x%08x chunk %u\n", val, chunk);
> `write %#08"PRIx32" chunk`
Done
https://review.coreboot.org/c/flashrom/+/73037/comment/3e0189e2_ed0b7364
PS5, Line 99: msg_pdbg2("asm106x read 0x%08x chunk %u\n", val, chunk);
> `read %#08"PRIx32" chunk`
Done
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