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[S] Change in flashrom[master]: jedec.c: Rename func to jedec_write_page()
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Edward O'Callaghan. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73282 ) Change subject: jedec.c: Rename func to jedec_write_page() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/73282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1be83d5974e305bddceaa34b64e982b774ade0d2 Gerrit-Change-Number: 73282 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Feb 2023 10:20:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: jedec.c: Drop branching non-zero programmer_delay() operands
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72692 ) Change subject: jedec.c: Drop branching non-zero programmer_delay() operands ...................................................................... jedec.c: Drop branching non-zero programmer_delay() operands The programmer_delay() function is already tolerant upon zero delay values and will simply just return with a NOP. Therefore there is no need to branch. Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72692 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> --- M jedec.c 1 file changed, 23 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Thomas Heijligen: Looks good to me, approved diff --git a/jedec.c b/jedec.c index 6ae767a..f9442ec 100644 --- a/jedec.c +++ b/jedec.c @@ -43,8 +43,7 @@ tmp1 = chip_readb(flash, dst) & 0x40; while (i++ < 0xFFFFFFF) { - if (delay) - programmer_delay(flash, delay); + programmer_delay(flash, delay); tmp2 = chip_readb(flash, dst) & 0x40; if (tmp1 == tmp2) { break; @@ -203,8 +202,7 @@ * mode completely. Allow the chip to finish this before seeing a * reset command. */ - if (probe_timing_enter) - programmer_delay(flash, probe_timing_enter); + programmer_delay(flash, probe_timing_enter); /* Reset chip to a clean slate */ if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); @@ -215,8 +213,7 @@ programmer_delay(flash, 10); } chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); - if (probe_timing_exit) - programmer_delay(flash, probe_timing_exit); + programmer_delay(flash, probe_timing_exit); /* Issue JEDEC Product ID Entry command */ chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); @@ -226,8 +223,7 @@ if (probe_timing_enter) programmer_delay(flash, 10); chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); - if (probe_timing_enter) - programmer_delay(flash, probe_timing_enter); + programmer_delay(flash, probe_timing_enter); /* Read product ID */ id1 = chip_readb(flash, bios + (0x00 << shifted)); @@ -257,8 +253,7 @@ programmer_delay(flash, 10); } chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); - if (probe_timing_exit) - programmer_delay(flash, probe_timing_exit); + programmer_delay(flash, probe_timing_exit); msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); if (!oddparity(id1)) -- To view, visit https://review.coreboot.org/c/flashrom/+/72692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Gerrit-Change-Number: 72692 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: jedec.c: Drop branching non-zero programmer_delay() operands
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Edward O'Callaghan. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72692 ) Change subject: jedec.c: Drop branching non-zero programmer_delay() operands ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e Gerrit-Change-Number: 72692 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 27 Feb 2023 10:19:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in flashrom[master]: ch347_spi: Add initial support for the WCH CH347
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70573 ) Change subject: ch347_spi: Add initial support for the WCH CH347 ...................................................................... ch347_spi: Add initial support for the WCH CH347 Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src(a)posteo.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS M Makefile A ch347_spi.c M flashrom.8.tmpl M include/programmer.h M meson.build M meson_options.txt M programmer_table.c M test_build.sh 9 files changed, 413 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index d1c4629..03f12b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -122,6 +122,11 @@ S: Maintained F: sb600spi.c +CH347 +M: Nicholas Chin <nic.c3.14(a)gmail.com> +S: Maintained +F: ch347_spi.c + I2C PROGRAMMERS M: Peter Marheine <pmarheine(a)chromium.org> S: Supported diff --git a/Makefile b/Makefile index a7200dd..5283fea 100644 --- a/Makefile +++ b/Makefile @@ -157,6 +157,7 @@ DEPENDS_ON_LIBUSB1 := \ CONFIG_CH341A_SPI \ + CONFIG_CH347_SPI \ CONFIG_DEDIPROG \ CONFIG_DEVELOPERBOX_SPI \ CONFIG_DIGILENT_SPI \ @@ -521,6 +522,9 @@ # Winchiphead CH341A CONFIG_CH341A_SPI ?= yes +# Winchiphead CH347 +CONFIG_CH347_SPI ?= yes + # Digilent Development board JTAG CONFIG_DIGILENT_SPI ?= yes @@ -814,6 +818,11 @@ ACTIVE_PROGRAMMERS += ch341a_spi endif +ifeq ($(CONFIG_CH347_SPI), yes) +FEATURE_FLAGS += -D'CONFIG_CH347_SPI=1' +PROGRAMMER_OBJS += ch347_spi.o +endif + ifeq ($(CONFIG_DIGILENT_SPI), yes) FEATURE_FLAGS += -D'CONFIG_DIGILENT_SPI=1' PROGRAMMER_OBJS += digilent_spi.o diff --git a/ch347_spi.c b/ch347_spi.c new file mode 100644 index 0000000..c3326b0 --- /dev/null +++ b/ch347_spi.c @@ -0,0 +1,345 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2022 Nicholas Chin <nic.c3.14(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <stdlib.h> +#include <libusb.h> +#include "platform.h" +#include "programmer.h" +#include "flash.h" + +#define CH347_CMD_SPI_SET_CFG 0xC0 +#define CH347_CMD_SPI_CS_CTRL 0xC1 +#define CH347_CMD_SPI_OUT_IN 0xC2 +#define CH347_CMD_SPI_IN 0xC3 +#define CH347_CMD_SPI_OUT 0xC4 +#define CH347_CMD_SPI_GET_CFG 0xCA + +#define CH347_CS_ASSERT 0x00 +#define CH347_CS_DEASSERT 0x40 +#define CH347_CS_CHANGE 0x80 +#define CH347_CS_IGNORE 0x00 + +#define WRITE_EP 0x06 +#define READ_EP 0x86 + +#define MODE_1_IFACE 2 +#define MODE_2_IFACE 1 + +/* The USB descriptor says the max transfer size is 512 bytes, but the + * vendor driver only seems to transfer a maximum of 510 bytes at once, + * leaving 507 bytes for data as the command + length take up 3 bytes + */ +#define CH347_PACKET_SIZE 510 +#define CH347_MAX_DATA_LEN (CH347_PACKET_SIZE - 3) + +struct ch347_spi_data { + struct libusb_device_handle *handle; +}; + +/* TODO: Add support for HID mode */ +static const struct dev_entry devs_ch347_spi[] = { + {0x1A86, 0x55DB, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, + {0} +}; + +static int ch347_spi_shutdown(void *data) +{ + struct ch347_spi_data *ch347_data = data; + + /* TODO: Set this depending on the mode */ + int spi_interface = MODE_1_IFACE; + libusb_release_interface(ch347_data->handle, spi_interface); + libusb_attach_kernel_driver(ch347_data->handle, spi_interface); + libusb_close(ch347_data->handle); + libusb_exit(NULL); + + free(data); + return 0; +} + +static int ch347_cs_control(struct ch347_spi_data *ch347_data, uint8_t cs1, uint8_t cs2) +{ + uint8_t cmd[13] = { + [0] = CH347_CMD_SPI_CS_CTRL, + /* payload length, uint16 LSB: 10 */ + [1] = 10, + [3] = cs1, + [8] = cs2 + }; + + int32_t ret = libusb_bulk_transfer(ch347_data->handle, WRITE_EP, cmd, sizeof(cmd), NULL, 1000); + if (ret < 0) { + msg_perr("Could not change CS!\n"); + return -1; + } + return 0; +} + + +static int ch347_write(struct ch347_spi_data *ch347_data, unsigned int writecnt, const uint8_t *writearr) +{ + unsigned int data_len; + int packet_len; + int transferred; + int ret; + uint8_t resp_buf[4] = {0}; + uint8_t buffer[CH347_PACKET_SIZE] = {0}; + unsigned int bytes_written = 0; + + while (bytes_written < writecnt) { + data_len = min(CH347_MAX_DATA_LEN, writecnt - bytes_written ); + packet_len = data_len + 3; + + buffer[0] = CH347_CMD_SPI_OUT; + buffer[1] = (data_len) & 0xFF; + buffer[2] = ((data_len) & 0xFF00) >> 8; + memcpy(buffer + 3, writearr + bytes_written, data_len); + + ret = libusb_bulk_transfer(ch347_data->handle, WRITE_EP, buffer, packet_len, &transferred, 1000); + if (ret < 0 || transferred != packet_len) { + msg_perr("Could not send write command\n"); + return -1; + } + + ret = libusb_bulk_transfer(ch347_data->handle, READ_EP, resp_buf, sizeof(resp_buf), NULL, 1000); + if (ret < 0) { + msg_perr("Could not receive write command response\n"); + return -1; + } + bytes_written += data_len; + } + return 0; +} + +static int ch347_read(struct ch347_spi_data *ch347_data, unsigned int readcnt, uint8_t *readarr) +{ + uint8_t *read_ptr = readarr; + int ret; + int transferred; + unsigned int bytes_read = 0; + uint8_t buffer[CH347_PACKET_SIZE] = {0}; + uint8_t command_buf[7] = { + [0] = CH347_CMD_SPI_IN, + [1] = 4, + [2] = 0, + [3] = readcnt & 0xFF, + [4] = (readcnt & 0xFF00) >> 8, + [5] = (readcnt & 0xFF0000) >> 16, + [6] = (readcnt & 0xFF000000) >> 24 + }; + + ret = libusb_bulk_transfer(ch347_data->handle, WRITE_EP, command_buf, sizeof(command_buf), &transferred, 1000); + if (ret < 0 || transferred != sizeof(command_buf)) { + msg_perr("Could not send read command\n"); + return -1; + } + + while (bytes_read < readcnt) { + ret = libusb_bulk_transfer(ch347_data->handle, READ_EP, buffer, CH347_PACKET_SIZE, &transferred, 1000); + if (ret < 0) { + msg_perr("Could not read data\n"); + return -1; + } + if (transferred > CH347_PACKET_SIZE) { + msg_perr("libusb bug: bytes received overflowed buffer\n"); + return -1; + } + /* Response: u8 command, u16 data length, then the data that was read */ + if (transferred < 3) { + msg_perr("CH347 returned an invalid response to read command\n"); + return -1; + } + int ch347_data_length = read_le16(buffer, 1); + if (transferred - 3 < ch347_data_length) { + msg_perr("CH347 returned less data than data length header indicates\n"); + return -1; + } + bytes_read += ch347_data_length; + if (bytes_read > readcnt) { + msg_perr("CH347 returned more bytes than requested\n"); + return -1; + } + memcpy(read_ptr, buffer + 3, ch347_data_length); + read_ptr += ch347_data_length; + } + return 0; +} + +static int ch347_spi_send_command(const struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +{ + struct ch347_spi_data *ch347_data = flash->mst->spi.data; + int ret = 0; + + ch347_cs_control(ch347_data, CH347_CS_ASSERT | CH347_CS_CHANGE, CH347_CS_IGNORE); + if (writecnt) { + ret = ch347_write(ch347_data, writecnt, writearr); + if (ret < 0) { + msg_perr("CH347 write error\n"); + return -1; + } + } + if (readcnt) { + ret = ch347_read(ch347_data, readcnt, readarr); + if (ret < 0) { + msg_perr("CH347 read error\n"); + return -1; + } + } + ch347_cs_control(ch347_data, CH347_CS_DEASSERT | CH347_CS_CHANGE, CH347_CS_IGNORE); + + return 0; +} + +static int32_t ch347_spi_config(struct ch347_spi_data *ch347_data, uint8_t divisor) +{ + int32_t ret; + uint8_t buff[29] = { + [0] = CH347_CMD_SPI_SET_CFG, + [1] = (sizeof(buff) - 3) & 0xFF, + [2] = ((sizeof(buff) - 3) & 0xFF00) >> 8, + /* Not sure what these two bytes do, but the vendor + * drivers seem to unconditionally set these values + */ + [5] = 4, + [6] = 1, + /* Clock polarity: bit 1 */ + [9] = 0, + /* Clock phase: bit 0 */ + [11] = 0, + /* Another mystery byte */ + [14] = 2, + /* Clock divisor: bits 5:3 */ + [15] = (divisor & 0x7) << 3, + /* Bit order: bit 7, 0=MSB */ + [17] = 0, + /* Yet another mystery byte */ + [19] = 7, + /* CS polarity: bit 7 CS2, bit 6 CS1. 0 = active low */ + [24] = 0 + }; + + ret = libusb_bulk_transfer(ch347_data->handle, WRITE_EP, buff, sizeof(buff), NULL, 1000); + if (ret < 0) { + msg_perr("Could not configure SPI interface\n"); + } + + /* FIXME: Not sure if the CH347 sends error responses for + * invalid config data, if so the code should check + */ + ret = libusb_bulk_transfer(ch347_data->handle, READ_EP, buff, sizeof(buff), NULL, 1000); + if (ret < 0) { + msg_perr("Could not receive configure SPI command response\n"); + } + return ret; +} + +static const struct spi_master spi_master_ch347_spi = { + .features = SPI_MASTER_4BA, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = ch347_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, + .shutdown = ch347_spi_shutdown, + .probe_opcode = default_spi_probe_opcode, +}; + +/* Largely copied from ch341a_spi.c */ +static int ch347_spi_init(const struct programmer_cfg *cfg) +{ + struct ch347_spi_data *ch347_data = calloc(1, sizeof(*ch347_data)); + if (!ch347_data) { + msg_perr("Could not allocate space for SPI data\n"); + return 1; + } + + int32_t ret = libusb_init(NULL); + if (ret < 0) { + msg_perr("Could not initialize libusb!\n"); + free(ch347_data); + return 1; + } + + /* Enable information, warning, and error messages (only). */ +#if LIBUSB_API_VERSION < 0x01000106 + libusb_set_debug(NULL, 3); +#else + libusb_set_option(NULL, LIBUSB_OPTION_LOG_LEVEL, LIBUSB_LOG_LEVEL_INFO); +#endif + + uint16_t vid = devs_ch347_spi[0].vendor_id; + uint16_t pid = devs_ch347_spi[0].device_id; + ch347_data->handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + if (ch347_data->handle == NULL) { + msg_perr("Couldn't open device %04x:%04x.\n", vid, pid); + free(ch347_data); + return 1; + } + + /* TODO: set based on mode */ + /* Mode 1 uses interface 2 for the SPI interface */ + int spi_interface = MODE_1_IFACE; + + ret = libusb_detach_kernel_driver(ch347_data->handle, spi_interface); + if (ret != 0 && ret != LIBUSB_ERROR_NOT_FOUND) + msg_pwarn("Cannot detach the existing USB driver. Claiming the interface may fail. %s\n", + libusb_error_name(ret)); + + ret = libusb_claim_interface(ch347_data->handle, spi_interface); + if (ret != 0) { + msg_perr("Failed to claim interface 2: '%s'\n", libusb_error_name(ret)); + goto error_exit; + } + + struct libusb_device *dev; + if (!(dev = libusb_get_device(ch347_data->handle))) { + msg_perr("Failed to get device from device handle.\n"); + goto error_exit; + } + + struct libusb_device_descriptor desc; + ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { + msg_perr("Failed to get device descriptor: '%s'\n", libusb_error_name(ret)); + goto error_exit; + } + + msg_pdbg("Device revision is %d.%01d.%01d\n", + (desc.bcdDevice >> 8) & 0x00FF, + (desc.bcdDevice >> 4) & 0x000F, + (desc.bcdDevice >> 0) & 0x000F); + + /* TODO: add programmer cfg for things like CS pin and divisor */ + if (ch347_spi_config(ch347_data, 2) < 0) + goto error_exit; + + return register_spi_master(&spi_master_ch347_spi, ch347_data); + +error_exit: + ch347_spi_shutdown(ch347_data); + return 1; +} + +const struct programmer_entry programmer_ch347_spi = { + .name = "ch347_spi", + .type = USB, + .devs.dev = devs_ch347_spi, + .init = ch347_spi_init, +}; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index dd4864d..d740db8 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -417,6 +417,8 @@ .sp .BR "* ch341a_spi" " (for SPI flash ROMs attached to WCH CH341A)" .sp +.BR "* ch347_spi" " (for SPI flash ROMs attached to WCH CH347)" +.sp .BR "* digilent_spi" " (for SPI flash ROMs attached to iCEblink40 development boards)" .sp .BR "* jlink_spi" " (for SPI flash ROMs attached to SEGGER J-Link and compatible devices)" @@ -1368,6 +1370,10 @@ The WCH CH341A programmer does not support any parameters currently. SPI frequency is fixed at 2 MHz, and CS0 is used as per the device. .SS +.BR "ch347_spi " programmer +The WCH CH347 programmer does not currently support any parameters. SPI frequency is fixed at 2 MHz, and CS0 is +used as per the device. +.SS .BR "ni845x_spi " programmer .IP An optional diff --git a/include/programmer.h b/include/programmer.h index 19363c2..f72f1d7 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -61,6 +61,7 @@ extern const struct programmer_entry programmer_atavia; extern const struct programmer_entry programmer_buspirate_spi; extern const struct programmer_entry programmer_ch341a_spi; +extern const struct programmer_entry programmer_ch347_spi; extern const struct programmer_entry programmer_dediprog; extern const struct programmer_entry programmer_developerbox; extern const struct programmer_entry programmer_digilent_spi; diff --git a/meson.build b/meson.build index 83fc120..d20f24c 100644 --- a/meson.build +++ b/meson.build @@ -201,6 +201,12 @@ 'test_srcs' : files('tests/ch341a_spi.c'), 'flags' : [ '-DCONFIG_CH341A_SPI=1' ], }, + 'ch347_spi' : { + 'deps' : [ libusb1 ], + 'groups' : [ group_usb, group_external ], + 'srcs' : files('ch347_spi.c'), + 'flags' : [ '-DCONFIG_CH347_SPI=1' ], + }, 'dediprog' : { 'deps' : [ libusb1 ], 'groups' : [ group_usb, group_external ], diff --git a/meson_options.txt b/meson_options.txt index 10427c8..307b551 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -10,7 +10,7 @@ 'auto', 'all', 'group_internal', 'group_external', 'group_ftdi', 'group_i2c', 'group_jlink', 'group_pci', 'group_serial', 'group_usb', - 'asm106x', 'atahpt', 'atapromise', 'atavia', 'buspirate_spi', 'ch341a_spi', 'dediprog', + 'asm106x', 'atahpt', 'atapromise', 'atavia', 'buspirate_spi', 'ch341a_spi', 'ch347_spi','dediprog', 'developerbox_spi', 'digilent_spi', 'dirtyjtag_spi', 'drkaiser', 'dummy', 'ft2232_spi', 'gfxnvidia', 'internal', 'it8212', 'jlink_spi', 'linux_mtd', 'linux_spi', 'mediatek_i2c_spi', 'mstarddc_spi', 'nic3com', 'nicintel', 'nicintel_eeprom', 'nicintel_spi', 'nicnatsemi', diff --git a/programmer_table.c b/programmer_table.c index 0935167..79acd77 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -156,6 +156,10 @@ &programmer_ch341a_spi, #endif +#if CONFIG_CH347_SPI == 1 + &programmer_ch347_spi, +#endif + #if CONFIG_DIGILENT_SPI == 1 &programmer_digilent_spi, #endif diff --git a/test_build.sh b/test_build.sh index 0e9d704..9b490dc 100755 --- a/test_build.sh +++ b/test_build.sh @@ -10,15 +10,15 @@ PICKIT2_SPI STLINKV3_SPI PARADE_LSPCON MEDIATEK_I2C_SPI REALTEK_MST_I2C_SPI DUMMY \ DRKAISER NICREALTEK NICNATSEMI NICINTEL NICINTEL_SPI NICINTEL_EEPROM OGP_SPI \ BUSPIRATE_SPI DEDIPROG DEVELOPERBOX_SPI SATAMV LINUX_MTD LINUX_SPI IT8212 \ - CH341A_SPI DIGILENT_SPI DIRTYJTAG_SPI JLINK_SPI ASM106X" + CH341A_SPI CH347_SPI DIGILENT_SPI DIRTYJTAG_SPI JLINK_SPI ASM106X" -meson_programmer_opts="all auto group_ftdi group_i2c group_jlink group_pci group_serial group_usb \ - atahpt atapromise atavia buspirate_spi ch341a_spi dediprog developerbox_spi \ - digilent_spi dirtyjtag_spi drkaiser dummy ft2232_spi gfxnvidia internal it8212 \ - jlink_spi linux_mtd linux_spi parade_lspcon mediatek_i2c_spi mstarddc_spi \ - nic3com nicintel nicintel_eeprom nicintel_spi nicnatsemi nicrealtek \ - ogp_spi pickit2_spi pony_spi raiden_debug_spi rayer_spi realtek_mst_i2c_spi \ - satamv satasii serprog stlinkv3_spi usbblaster_spi asm106x" +meson_programmer_opts="all auto group_ftdi group_i2c group_jlink group_pci group_serial group_usb \ + atahpt atapromise atavia buspirate_spi ch341a_spi ch347_spi dediprog \ + developerbox_spi digilent_spi dirtyjtag_spi drkaiser dummy ft2232_spi \ + gfxnvidia internal it8212 jlink_spi linux_mtd linux_spi parade_lspcon \ + mediatek_i2c_spi mstarddc_spi nic3com nicintel nicintel_eeprom nicintel_spi \ + nicnatsemi nicrealtek ogp_spi pickit2_spi pony_spi raiden_debug_spi rayer_spi \ + realtek_mst_i2c_spi satamv satasii serprog stlinkv3_spi usbblaster_spi asm106x" if [ "$(basename "${CC}")" = "ccc-analyzer" ] || [ -n "${COVERITY_OUTPUT}" ]; then -- To view, visit https://review.coreboot.org/c/flashrom/+/70573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Gerrit-Change-Number: 70573 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: qianfan <qianfanguijin(a)163.com> Gerrit-MessageType: merged

1 0

[L] Change in flashrom[master]: ch347_spi: Add initial support for the WCH CH347
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Felix Singer, Angel Pons, qianfan, Nicholas Chin. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70573 ) Change subject: ch347_spi: Add initial support for the WCH CH347 ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Patchset: PS9: Manual rebase -- To view, visit https://review.coreboot.org/c/flashrom/+/70573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Gerrit-Change-Number: 70573 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 27 Feb 2023 10:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in flashrom[master]: ch347_spi: Add initial support for the WCH CH347
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Felix Singer, Angel Pons, qianfan, Nicholas Chin. Thomas Heijligen has uploaded a new patch set (#9) to the change originally created by Nicholas Chin. ( https://review.coreboot.org/c/flashrom/+/70573 ) Change subject: ch347_spi: Add initial support for the WCH CH347 ...................................................................... ch347_spi: Add initial support for the WCH CH347 Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba --- M MAINTAINERS M Makefile A ch347_spi.c M flashrom.8.tmpl M include/programmer.h M meson.build M meson_options.txt M programmer_table.c M test_build.sh 9 files changed, 410 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/70573/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/70573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Gerrit-Change-Number: 70573 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in flashrom[master]: asm106x: add programmer for ASM106x SATA controllers
by Thomas Heijligen (Code Review) 27 Feb '23

27 Feb '23

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/73037 ) Change subject: asm106x: add programmer for ASM106x SATA controllers ...................................................................... asm106x: add programmer for ASM106x SATA controllers The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> --- M Makefile A asm106x.c M flashrom.8.tmpl M include/programmer.h M meson.build M meson_options.txt M programmer_table.c M test_build.sh 8 files changed, 215 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved diff --git a/Makefile b/Makefile index 69818ce..a7200dd 100644 --- a/Makefile +++ b/Makefile @@ -137,6 +137,7 @@ CONFIG_SATAMV \ DEPENDS_ON_LIBPCI := \ + CONFIG_ASM106X \ CONFIG_ATAHPT \ CONFIG_ATAPROMISE \ CONFIG_ATAVIA \ @@ -437,6 +438,9 @@ # Always enable SiI SATA controllers for now. CONFIG_SATASII ?= yes +# ASMedia ASM106x +CONFIG_ASM106X ?= yes + # Highpoint (HPT) ATA/RAID controller support. # IMPORTANT: This code is not yet working! CONFIG_ATAHPT ?= no @@ -642,6 +646,12 @@ ACTIVE_PROGRAMMERS += satasii endif +ifeq ($(CONFIG_ASM106X), yes) +FEATURE_FLAGS += -D'CONFIG_ASM106X=1' +PROGRAMMER_OBJS += asm106x.o +ACTIVE_PROGRAMMERS += asm106x +endif + ifeq ($(CONFIG_ATAHPT), yes) FEATURE_FLAGS += -D'CONFIG_ATAHPT=1' PROGRAMMER_OBJS += atahpt.o diff --git a/asm106x.c b/asm106x.c new file mode 100644 index 0000000..fe35f94 --- /dev/null +++ b/asm106x.c @@ -0,0 +1,156 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2023 Alex Badea <vamposdecampos(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include "programmer.h" +#include "platform/pci.h" + +#define PCI_VENDOR_ID_ASMEDIA 0x1b21 + +#define ASM106X_REG_DATA 0xf0 +#define ASM106X_REG_CTRL 0xf4 +#define ASM106X_CTRL_RUN 0x20 /* SPI master is running */ +#define ASM106X_CTRL_CSN 0x10 /* CS_n pin output */ +#define ASM106X_CTRL_WRITE 0x08 /* 0=read, 1=write */ +#define ASM106X_CTRL_MASK 0xc0 /* unknown, untouched */ + +struct asm106x_data { + struct pci_dev *pci; +}; + +static const struct dev_entry asm106x_devs[] = { + {PCI_VENDOR_ID_ASMEDIA, 0x0612, OK, "ASMedia", "ASM106x"}, + + {0}, +}; + +static int asm106x_wait_ready(struct pci_dev *pci, uint8_t *pval) +{ + unsigned int timeout = 100; + uint8_t val; + + while (timeout) { + val = pci_read_byte(pci, ASM106X_REG_CTRL); + msg_pdbg2("asm106x status %#02"PRIx8" tries %d\n", val, timeout); + if (!(val & ASM106X_CTRL_RUN)) { + if (pval) + *pval = val; + return 0; + } + default_delay(10); + timeout--; + } + + msg_pdbg("asm106x timed out, ctrl %#02"PRIx8"\n", val); + return 1; +} + + +static int asm106x_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + struct asm106x_data *data = flash->mst->spi.data; + uint8_t ctrl; + int rv = 1; + + msg_pdbg2("asm106x command: wr %d rd %d\n", writecnt, readcnt); + if (asm106x_wait_ready(data->pci, &ctrl)) + return 1; + ctrl &= ASM106X_CTRL_MASK; + + while (writecnt) { + const unsigned int chunk = min(writecnt, 4); + uint32_t val = 0; + + for (int k = chunk-1; k >= 0; k--) + val = (val << 8) | writearr[k]; + msg_pdbg2("asm106x write %#08"PRIx32" chunk %u\n", val, chunk); + pci_write_long(data->pci, ASM106X_REG_DATA, val); + pci_write_byte(data->pci, ASM106X_REG_CTRL, + ctrl | ASM106X_CTRL_RUN | ASM106X_CTRL_WRITE | chunk); + if (asm106x_wait_ready(data->pci, NULL)) + goto out; + writecnt -= chunk; + writearr += chunk; + } + while (readcnt) { + const unsigned int chunk = min(readcnt, 4); + + pci_write_byte(data->pci, ASM106X_REG_CTRL, + ctrl | ASM106X_CTRL_RUN | chunk); + if (asm106x_wait_ready(data->pci, NULL)) + goto out; + + uint32_t val = pci_read_long(data->pci, ASM106X_REG_DATA); + msg_pdbg2("asm106x read %#08"PRIx32" chunk %u\n", val, chunk); + for (unsigned int k = 0; k < chunk; k++) { + readarr[k] = val & 0xff; + val >>= 8; + } + readcnt -= chunk; + readarr += chunk; + } + + rv = 0; +out: + pci_write_byte(data->pci, ASM106X_REG_CTRL, ctrl | ASM106X_CTRL_CSN); + return rv; +} + +static int asm106x_shutdown(void *data) +{ + free(data); + return 0; +} + +static const struct spi_master asm106x_spi_master = { + .features = SPI_MASTER_4BA, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = asm106x_command, + .shutdown = asm106x_shutdown, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .probe_opcode = default_spi_probe_opcode, +}; + +static int asm106x_init(const struct programmer_cfg *cfg) +{ + struct pci_dev *pci; + struct asm106x_data *data; + + /* TODO: no BAR required (just config space) */ + pci = pcidev_init(cfg, asm106x_devs, PCI_ROM_ADDRESS); + if (!pci) + return 1; + + data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("cannot allocate memory for asm106x_data\n"); + return 1; + } + data->pci = pci; + return register_spi_master(&asm106x_spi_master, data); +} + +const struct programmer_entry programmer_asm106x = { + .name = "asm106x", + .type = PCI, + .devs.dev = asm106x_devs, + .init = asm106x_init, +}; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0eabee5..dd4864d 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -433,6 +433,8 @@ .sp .BR "* dirtyjtag_spi" " (for SPI flash ROMs attached to DirtyJTAG-compatible devices)" .sp +.BR "* asm106x" " (for SPI flash ROMs attached to ASM106x PCIe SATA controllers)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1685,7 +1687,8 @@ needs no access permissions at all. .sp .BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", " -.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt ", " atavia " and " atapromise +.BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " asm106x ", " +.BR atahpt ", " atavia " and " atapromise have to be run as superuser/root, and need additional raw access permission. .sp .BR serprog ", " buspirate_spi ", " dediprog ", " usbblaster_spi ", " ft2232_spi ", " pickit2_spi ", " \ diff --git a/include/programmer.h b/include/programmer.h index 2a4ca76..19363c2 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -55,6 +55,7 @@ extern const size_t programmer_table_size; /* programmer drivers */ +extern const struct programmer_entry programmer_asm106x; extern const struct programmer_entry programmer_atahpt; extern const struct programmer_entry programmer_atapromise; extern const struct programmer_entry programmer_atavia; diff --git a/meson.build b/meson.build index baa1084..83fc120 100644 --- a/meson.build +++ b/meson.build @@ -156,6 +156,13 @@ # 'active' : boolean, # added on runtime # } programmer = { + 'asm106x' : { + 'systems' : systems_hwaccess, + 'deps' : [ libpci ], + 'groups' : [ group_pci, group_internal ], + 'srcs' : files('asm106x.c', 'pcidev.c'), + 'flags' : [ '-DCONFIG_ASM106X=1' ], + }, 'atahpt' : { 'systems' : systems_hwaccess, 'cpu_families' : cpus_port_io, diff --git a/meson_options.txt b/meson_options.txt index 9dcebdc..10427c8 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -10,11 +10,11 @@ 'auto', 'all', 'group_internal', 'group_external', 'group_ftdi', 'group_i2c', 'group_jlink', 'group_pci', 'group_serial', 'group_usb', - 'atahpt', 'atapromise', 'atavia', 'buspirate_spi', 'ch341a_spi', 'dediprog', 'developerbox_spi', - 'digilent_spi', 'dirtyjtag_spi', 'drkaiser', 'dummy', 'ft2232_spi', 'gfxnvidia', 'internal', 'it8212', - 'jlink_spi', 'linux_mtd', 'linux_spi', 'mediatek_i2c_spi', 'mstarddc_spi', 'nic3com', 'nicintel', - 'nicintel_eeprom', 'nicintel_spi', 'nicnatsemi', 'nicrealtek', 'ogp_spi', 'parade_lspcon', - 'pickit2_spi', 'pony_spi', 'raiden_debug_spi', 'rayer_spi', 'realtek_mst_i2c_spi', 'satamv', - 'satasii', 'serprog', 'stlinkv3_spi', 'usbblaster_spi', + 'asm106x', 'atahpt', 'atapromise', 'atavia', 'buspirate_spi', 'ch341a_spi', 'dediprog', + 'developerbox_spi', 'digilent_spi', 'dirtyjtag_spi', 'drkaiser', 'dummy', 'ft2232_spi', + 'gfxnvidia', 'internal', 'it8212', 'jlink_spi', 'linux_mtd', 'linux_spi', 'mediatek_i2c_spi', + 'mstarddc_spi', 'nic3com', 'nicintel', 'nicintel_eeprom', 'nicintel_spi', 'nicnatsemi', + 'nicrealtek', 'ogp_spi', 'parade_lspcon', 'pickit2_spi', 'pony_spi', 'raiden_debug_spi', + 'rayer_spi', 'realtek_mst_i2c_spi', 'satamv', 'satasii', 'serprog', 'stlinkv3_spi', 'usbblaster_spi', ], description: 'Active programmers') option('llvm_cov', type : 'feature', value : 'disabled', description : 'build for llvm code coverage') diff --git a/programmer_table.c b/programmer_table.c index d58a155..0935167 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -52,6 +52,10 @@ &programmer_satasii, #endif +#if CONFIG_ASM106X == 1 + &programmer_asm106x, +#endif + #if CONFIG_ATAHPT == 1 &programmer_atahpt, #endif diff --git a/test_build.sh b/test_build.sh index c2f74d2..0e9d704 100755 --- a/test_build.sh +++ b/test_build.sh @@ -10,7 +10,7 @@ PICKIT2_SPI STLINKV3_SPI PARADE_LSPCON MEDIATEK_I2C_SPI REALTEK_MST_I2C_SPI DUMMY \ DRKAISER NICREALTEK NICNATSEMI NICINTEL NICINTEL_SPI NICINTEL_EEPROM OGP_SPI \ BUSPIRATE_SPI DEDIPROG DEVELOPERBOX_SPI SATAMV LINUX_MTD LINUX_SPI IT8212 \ - CH341A_SPI DIGILENT_SPI DIRTYJTAG_SPI JLINK_SPI" + CH341A_SPI DIGILENT_SPI DIRTYJTAG_SPI JLINK_SPI ASM106X" meson_programmer_opts="all auto group_ftdi group_i2c group_jlink group_pci group_serial group_usb \ atahpt atapromise atavia buspirate_spi ch341a_spi dediprog developerbox_spi \ @@ -18,7 +18,7 @@ jlink_spi linux_mtd linux_spi parade_lspcon mediatek_i2c_spi mstarddc_spi \ nic3com nicintel nicintel_eeprom nicintel_spi nicnatsemi nicrealtek \ ogp_spi pickit2_spi pony_spi raiden_debug_spi rayer_spi realtek_mst_i2c_spi \ - satamv satasii serprog stlinkv3_spi usbblaster_spi" + satamv satasii serprog stlinkv3_spi usbblaster_spi asm106x" if [ "$(basename "${CC}")" = "ccc-analyzer" ] || [ -n "${COVERITY_OUTPUT}" ]; then -- To view, visit https://review.coreboot.org/c/flashrom/+/73037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Gerrit-Change-Number: 73037 Gerrit-PatchSet: 10 Gerrit-Owner: Alex Badea <vamposdecampos(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: MAINTAINERS: Update unit tests from Supported to Maintained
by Anastasia Klimchuk (Code Review) 27 Feb '23

27 Feb '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/73277 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: MAINTAINERS: Update unit tests from Supported to Maintained ...................................................................... MAINTAINERS: Update unit tests from Supported to Maintained Change-Id: I13853c6c48eb4054d2ed7d79bcfc768684914797 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73277 Reviewed-by: Thomas Heijligen <src(a)posteo.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 258a29f..d1c4629 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -150,7 +150,7 @@ UNIT TESTS M: Anastasia Klimchuk <aklm(a)chromium.org> -S: Supported +S: Maintained F: tests/ F: subprojects/cmocka.wrap -- To view, visit https://review.coreboot.org/c/flashrom/+/73277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13853c6c48eb4054d2ed7d79bcfc768684914797 Gerrit-Change-Number: 73277 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: libflashrom: Provide flashrom_flash_getname() API
by Edward O'Callaghan (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/73286 to look at the new patch set (#3). Change subject: libflashrom: Provide flashrom_flash_getname() API ...................................................................... libflashrom: Provide flashrom_flash_getname() API The libflashom API exposes a API to get the flash size however not the flash name. Change-Id: I3dc32e261e6d54230d93f06b91f723811792112a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M include/libflashrom.h M libflashrom.c M libflashrom.map 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/73286/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/73286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3dc32e261e6d54230d93f06b91f723811792112a Gerrit-Change-Number: 73286 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in flashrom[master]: meson make: use VERSION file
by Edward O'Callaghan (Code Review) 27 Feb '23

27 Feb '23

Attention is currently required from: Thomas Heijligen. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72657 ) Change subject: meson make: use VERSION file ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idc17eadb397b3c579bddfbf9ae6bf1b171f5dfb7 Gerrit-Change-Number: 72657 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Mon, 27 Feb 2023 05:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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