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[M] Change in flashrom[master]: flashrom: only perform WP unlock for write/erase operations
by Brian Norris (Code Review) 13 Jul '23

13 Jul '23

Attention is currently required from: Nikolai Artemiev. Brian Norris has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75991?usp=email ) Change subject: flashrom: only perform WP unlock for write/erase operations ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/75991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5dc66474a0b7969b51b86ac9f5daa2c95ae968f1 Gerrit-Change-Number: 75991 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 12 Jul 2023 22:41:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: Add XTX XT25F64B
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Attention is currently required from: Angel Pons, Thomas Heijligen, WereCatf. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58173?usp=email ) Change subject: flashchips: Add XTX XT25F64B ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Hello WereCatf, I am sorry that your patches got lost :( I mean this one and CB:58134. […] Okay, looks like you are busy or left, I updated the patchset and replaced func pointers with enums, also rebased. -- To view, visit https://review.coreboot.org/c/flashrom/+/58173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836 Gerrit-Change-Number: 58173 Gerrit-PatchSet: 3 Gerrit-Owner: WereCatf <werecatf(a)outlook.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: WereCatf <werecatf(a)outlook.com> Gerrit-Comment-Date: Wed, 12 Jul 2023 13:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: Add XTX XT25F64B
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Attention is currently required from: Angel Pons, Thomas Heijligen, WereCatf. Anastasia Klimchuk has uploaded a new patch set (#3) to the change originally created by WereCatf. ( https://review.coreboot.org/c/flashrom/+/58173?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: flashchips: Add XTX XT25F64B ...................................................................... flashchips: Add XTX XT25F64B Datasheet: http://file2.dzsc.com/product/19/06/22/216185_132959081.pdf Tested probe, read, erase and write with CH341a. Signed-off-by: Nita Vesa <werecatf(a)outlook.com> Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashchips.c M include/flashchips.h 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/58173/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/58173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836 Gerrit-Change-Number: 58173 Gerrit-PatchSet: 3 Gerrit-Owner: WereCatf <werecatf(a)outlook.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: WereCatf <werecatf(a)outlook.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashchips: Add support for PUYA P25Q40H
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Attention is currently required from: Anne Macedo. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/76251?usp=email ) Change subject: flashchips: Add support for PUYA P25Q40H ...................................................................... Patch Set 1: (5 comments) Patchset: PS1: Anne, thank you for your patch! I have few comments. If you have any questions, you are welcome to ask. File flashchips.c: https://review.coreboot.org/c/flashrom/+/76251/comment/378d4ce6_c0576523 : PS1, Line 13793: .manufacture_id = 0x85, : .model_id = 0x6013, These two ids should go to include/flashchips.h At the moment there is no section for Puya, so it needs to be added. There is a patch under review right now, which adds the Puya section and few ids (not the same, different chips), here is that patch CB:58134 I am not sure that original author of CB:58134 will return back, so it could be me finishing that patch. So maybe you can add Puya section and your ids into include/flashchips.h (using CB:58134 as example), and then I can rebase CB:58134 on the top of your patch. https://review.coreboot.org/c/flashrom/+/76251/comment/0c7d3b58_bcf5bb8a : PS1, Line 13797: .feature_bits = FEATURE_WRSR_WREN, It also supports FEATURE_OTP https://review.coreboot.org/c/flashrom/+/76251/comment/55426530_fa3b36aa : PS1, Line 13813: .eraseblocks = { {512 * 1024, 1} }, : .block_erase = SPI_BLOCK_ERASE_81, Command 81 is doing page erase for 256 bytes. This is the smallest eraseblock, should be the first (the current definition sets this as if it is full chip erase, which is not). And, there is a chip erase in the datasheet, command 60 or C7, these two should come last in the list. https://review.coreboot.org/c/flashrom/+/76251/comment/5d93e54b_d87aced9 : PS1, Line 13817: SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD I think this should be BP4, and same for the unlock -- To view, visit https://review.coreboot.org/c/flashrom/+/76251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I58c2c0467ef19f98b7435e84b6978550f029af70 Gerrit-Change-Number: 76251 Gerrit-PatchSet: 1 Gerrit-Owner: Anne Macedo <retpolanne(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anne Macedo <retpolanne(a)posteo.net> Gerrit-Comment-Date: Wed, 12 Jul 2023 10:08:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: add support for MX77L25650F chip
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68557?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips: add support for MX77L25650F chip ...................................................................... flashchips: add support for MX77L25650F chip Add initial support for Macronix MX77L25650F. Can read, write and erase the chip. Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Signed-off-by: Artur Kowalski <artur.kowalski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Signed-off-by: ServError <admin(a)serverror.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index b11c558..d1ce20d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10854,6 +10854,46 @@ .voltage = {2700, 3600}, }, + { + .vendor = "Macronix", + .name = "MX77L25650F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX77L25650F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: block WP, security register, configuration register */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + /* The ST M25P05 is a bit of a problem. It has the same ID as the * ST M25P05-A in RES mode, but supports only 128 byte writes instead * of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1 diff --git a/include/flashchips.h b/include/flashchips.h index dd0e835..3bbd573 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -531,6 +531,7 @@ #define MACRONIX_MX25U51245G 0x253a #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX25L6495F 0x9517 +#define MACRONIX_MX77L25650F 0x7519 #define MACRONIX_MX25R3235F 0x2816 #define MACRONIX_MX25R6435F 0x2817 -- To view, visit https://review.coreboot.org/c/flashrom/+/68557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Gerrit-Change-Number: 68557 Gerrit-PatchSet: 8 Gerrit-Owner: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: ServError <admin(a)serverror.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Artur Kowalski <arturkow2000(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashchips.c: Adding support for ISSI IS25WP020/40/80
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/75830?usp=email ) Change subject: flashchips.c: Adding support for ISSI IS25WP020/40/80 ...................................................................... flashchips.c: Adding support for ISSI IS25WP020/40/80 This patch added support for IS25WP020, IS25WP040, and IS25WP080 SPI flash chips. The datasheet for these chips can be found at: https://www.issi.com/WW/pdf/25WP016_080_040_020.pdf Tested read, write, and erase functions on IS25WP080. Test log: Write: https://paste.flashrom.org/view.php?id=3698 Write test 2: https://paste.flashrom.org/view.php?id=3699 Erase: https://paste.flashrom.org/view.php?id=3700 Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28 Signed-off-by: Ao Zhong <hacc1225(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 129 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 9b2a187..b11c558 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7767,6 +7767,48 @@ { .vendor = "ISSI", + .name = "IS25WP020", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP020, + .total_size = 256, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP032", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, @@ -7809,6 +7851,48 @@ { .vendor = "ISSI", + .name = "IS25WP040", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP040, + .total_size = 512, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP064", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, @@ -7851,6 +7935,48 @@ { .vendor = "ISSI", + .name = "IS25WP080", + .bustype = BUS_SPI, + .manufacture_id = ISSI_ID_SPI, + .model_id = ISSI_IS25WP080, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total; read 0x48; write 0x42 */ + /* QPI enable 0x35, disable 0xF5 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D7, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "ISSI", .name = "IS25WP128", .bustype = BUS_SPI, .manufacture_id = ISSI_ID_SPI, diff --git a/include/flashchips.h b/include/flashchips.h index 49e54fa..dd0e835 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -479,8 +479,11 @@ #define ISSI_IS25LP128 0x6018 #define ISSI_IS25LP256 0x6019 #define ISSI_IS25WP016 0x7015 +#define ISSI_IS25WP020 0x7012 #define ISSI_IS25WP032 0x7016 +#define ISSI_IS25WP040 0x7013 #define ISSI_IS25WP064 0x7017 +#define ISSI_IS25WP080 0x7014 #define ISSI_IS25WP128 0x7018 #define ISSI_IS25WP256 0x7019 #define ISSI_PMC_IS29GL032B 0xF9 -- To view, visit https://review.coreboot.org/c/flashrom/+/75830?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28 Gerrit-Change-Number: 75830 Gerrit-PatchSet: 6 Gerrit-Owner: Ao Zhong <hacc1225(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in flashrom[master]: MAINTAINERS: Add Anastasia Klimchuk for flashchips
by Anastasia Klimchuk (Code Review) 12 Jul '23

12 Jul '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/75895?usp=email ) Change subject: MAINTAINERS: Add Anastasia Klimchuk for flashchips ...................................................................... MAINTAINERS: Add Anastasia Klimchuk for flashchips Change-Id: I82049c6686b7199dec55082ab9cbe71bfa89d2d7 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75895 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Nikolai Artemiev: Looks good to me, approved build bot (Jenkins): Verified diff --git a/MAINTAINERS b/MAINTAINERS index 7699eca..e3aeef0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -97,6 +97,12 @@ F: erasure_layout* F: include/erasure_layout* +FLASHCHIPS +M: Anastasia Klimchuk <aklm(a)chromium.org> +S: Maintained +F: flashchips* +F: include/flashchips* + I2C HELPERS M: Peter Marheine <pmarheine(a)chromium.org> S: Supported -- To view, visit https://review.coreboot.org/c/flashrom/+/75895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I82049c6686b7199dec55082ab9cbe71bfa89d2d7 Gerrit-Change-Number: 75895 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashrom: only perform WP unlock for write/erase operations
by Edward O'Callaghan (Code Review) 11 Jul '23

11 Jul '23

Attention is currently required from: Brian Norris, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75991?usp=email ) Change subject: flashrom: only perform WP unlock for write/erase operations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/75991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5dc66474a0b7969b51b86ac9f5daa2c95ae968f1 Gerrit-Change-Number: 75991 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 11 Jul 2023 00:01:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in flashrom[master]: doc: Add new Development guidelines
by Peter Marheine (Code Review) 10 Jul '23

10 Jul '23

Attention is currently required from: Alexander Goncharov, Anastasia Klimchuk, Angel Pons, Edward O'Callaghan, Nikolai Artemiev, Stefan Reinauer, Swift Geek (Sebastian Grzywna), Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75906?usp=email ) Change subject: doc: Add new Development guidelines ...................................................................... Patch Set 5: Code-Review+2 (4 comments) File doc/dev_guide/development_guide.rst: https://review.coreboot.org/c/flashrom/+/75906/comment/94f860b3_c9c4888c : PS5, Line 161: approproately typo: appropriately https://review.coreboot.org/c/flashrom/+/75906/comment/deec150a_25262a4f : PS5, Line 235: -s If the commit is already signed-off, will this add another signoff (probably not intended), or will it avoid adding a new one? https://review.coreboot.org/c/flashrom/+/75906/comment/faaaf5be_3d899126 : PS5, Line 235: you typo: your File doc/dev_guide/development_guidelines.rst: https://review.coreboot.org/c/flashrom/+/75906/comment/0254372f_7d87ff4e : PS2, Line 7: Set up the git repository and dev environment > Renamed to development guide, I am happy to rename this doc! […] Fine by me; as long as the document title isn't overly specific (renaming it fixed that) and the section headings make sense (my earlier suggestions worked toward that) then it shouldn't be difficult to navigate. -- To view, visit https://review.coreboot.org/c/flashrom/+/75906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7fe9ab2e27fead8e795138294219b11240f15928 Gerrit-Change-Number: 75906 Gerrit-PatchSet: 5 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Mon, 10 Jul 2023 04:12:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: doc: Add documentation license
by Alexander Goncharov (Code Review) 07 Jul '23

07 Jul '23

Attention is currently required from: Anastasia Klimchuk, Patrick Georgi, Stefan Reinauer, Thomas Heijligen. Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75727?usp=email ) Change subject: doc: Add documentation license ...................................................................... Patch Set 3: Code-Review+1 (2 comments) File doc/documentation_license.rst: https://review.coreboot.org/c/flashrom/+/75727/comment/d4e08f92_57a3b7af : PS3, Line 2: flashrom documentation license > I don't think it's critical. […] My point is that we do not write "flashrom developers documentation" or "flashrom contact" because it's obvious that all stuff is related to flashrom and not coreboot or whatever. Also, it takes up more than one line in the toctree. But if everybody is fine with that, then I don't mind. https://review.coreboot.org/c/flashrom/+/75727/comment/b2dd3eba_b117490c : PS3, Line 5: doc/ > The way we did it for coreboot (and its wiki) was that every time we found a useful nugget of inform […] Thanks for the clarification! Then resolved. -- To view, visit https://review.coreboot.org/c/flashrom/+/75727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ied858b5f1e9c4a83a6eb21dcefb288c4474b08c0 Gerrit-Change-Number: 75727 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 07 Jul 2023 11:45:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Alexander Goncharov <chat(a)joursoir.net> Gerrit-MessageType: comment

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