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[L] Change in flashrom[main]: tests: Unit tests for erase function selection algo
by Anastasia Klimchuk (Code Review) 09 Nov '23

09 Nov '23

Attention is currently required from: Aarya, Anastasia Klimchuk, Edward O'Callaghan, Nikolai Artemiev, Simon Buhrow, Thomas Heijligen. Hello Aarya, Edward O'Callaghan, Simon Buhrow, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/67535?usp=email to look at the new patch set (#21). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tests: Unit tests for erase function selection algo ...................................................................... tests: Unit tests for erase function selection algo The test checks that algorithm for erase functions selection works and there are no regressions. Specifically, test contains an array of test cases. Each case initialises a given initial state of the memory for the mock chip, and layout regions on the chip, and then performs erase and write operations. At the end of operation, test asserts the following: - the state of mock chip memory is as expected, i.e. properly erased or written - erase blocks are invoked in expected order and expected number of them - chip operation (erase or write) returned 0. Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- A tests/erase_func_algo.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 751 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/67535/21 -- To view, visit https://review.coreboot.org/c/flashrom/+/67535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 21 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[main]: tests: Unit tests for erase function selection algo
by Peter Marheine (Code Review) 09 Nov '23

09 Nov '23

Attention is currently required from: Aarya, Anastasia Klimchuk, Edward O'Callaghan, Nikolai Artemiev, Simon Buhrow, Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67535?usp=email ) Change subject: tests: Unit tests for erase function selection algo ...................................................................... Patch Set 20: (1 comment) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/67535/comment/da1b0df1_37e050d4 : PS20, Line 62: struct test_case* current_test_case; /* Currently executed test case. */ Can this be const, or is there mutability hidden inside it? (If there is, can it be moved into this struct?) -- To view, visit https://review.coreboot.org/c/flashrom/+/67535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 20 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 08 Nov 2023 23:41:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[main]: spi25_statusreg: rename amic_a25l032 print to a generic name
by Alexander Goncharov (Code Review) 08 Nov '23

08 Nov '23

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78874?usp=email ) Change subject: spi25_statusreg: rename amic_a25l032 print to a generic name ...................................................................... Patch Set 1: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/78874/comment/22ce3a6d_29d91e09 : PS1, Line 1278: /* bit5: T/B, bit6: prot size */ > Is this comment useful? if yes, you can rename the function/enum but keep the comment Since we are using a function that contain a register name, I don't see any point in this comment `SEC_TB` = Sector Protect Size (SEC), Top/Bottom (TB) -- To view, visit https://review.coreboot.org/c/flashrom/+/78874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804 Gerrit-Change-Number: 78874 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 08 Nov 2023 17:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: Makefile: CONFIG_INTERNAL depends on raw mem access
by Alexander Goncharov (Code Review) 08 Nov '23

08 Nov '23

Attention is currently required from: Anastasia Klimchuk, Fabrice Fontaine, Thomas Heijligen. Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78930?usp=email ) Change subject: Makefile: CONFIG_INTERNAL depends on raw mem access ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thanks for the patch! Were you able to compile flashrom without errors after applying this patch? Do you need `internal` programmer support in your flashrom build? I'm asking that because I assume that you have compiled flashrom without it. Makefile [disables all drivers needing raw access](https://review.coreboot.org/plugins/gitiles/flashrom/+/refs/heads/m… on `sh` architecture (`build-end.log` says so). Back in the days when it was added in the commit 8d0d53fdd0 , the code marked `CONFIG_INTERNAL` option as unavailable. Then CB:22671 made compiling the internal programmer available only on x86 or mipsel. And eventually CB:61300 allowed compiling internal programmer for all Linux platforms. -- To view, visit https://review.coreboot.org/c/flashrom/+/78930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7610f5f7cc5b114ffa90d5752155acc8b6b7c9f7 Gerrit-Change-Number: 78930 Gerrit-PatchSet: 1 Gerrit-Owner: Fabrice Fontaine <fontaine.fabrice(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Fabrice Fontaine <fontaine.fabrice(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 08 Nov 2023 17:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: erasure_layout: Fix double invocation of erasers
by Alexander Goncharov (Code Review) 08 Nov '23

08 Nov '23

Attention is currently required from: Aarya, Anastasia Klimchuk, Sam McNally. Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77747?usp=email ) Change subject: erasure_layout: Fix double invocation of erasers ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS3: > Okay so I am deep into debugging https://ticket.coreboot. […] Yeah, I see that it's not related now. Thank you for delving into my problem :) This one is a good catch though, so it should definitely be merged! -- To view, visit https://review.coreboot.org/c/flashrom/+/77747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I92351eba0fd29114ce98b4a839358e92d176af28 Gerrit-Change-Number: 77747 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 08 Nov 2023 16:18:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Alexander Goncharov <chat(a)joursoir.net> Gerrit-MessageType: comment

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[L] Change in flashrom[main]: tests: Unit tests for erase function selection algo
by Anastasia Klimchuk (Code Review) 06 Nov '23

06 Nov '23

Attention is currently required from: Aarya, Edward O'Callaghan, Nikolai Artemiev, Peter Marheine, Simon Buhrow, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67535?usp=email ) Change subject: tests: Unit tests for erase function selection algo ...................................................................... Patch Set 20: (2 comments) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/67535/comment/7e3526cc_9be492c6 : PS3, Line 238: void **state > I think it's worth doing that, but you don't need to expose much detail. […] Peter, this is beautiful, thank you so much for the cool idea! I made an implementation, which is ready for review. I like that now every test case is an actual test (even two tests, one for erase and one for write). The surprising thing for me was that CMUnitTest needs to have a name explicitly initialised. If not, test is silently skipped (with no messages!). So I had 0 tests run until I got names for all of them! :) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/67535/comment/ff2e96e0_22e656bd : PS14, Line 61: struct test_case test_cases[TEST_CASES_NUM]; /* Data for running tests. */ > I'd prefer to make this a `const struct test_case *` just to capture that the test case data is immu […] The code has changed after I implemented your other comment, but as a part of it I removed `ind` (no longer needed) and now there is a pointer to `current_test_case`. -- To view, visit https://review.coreboot.org/c/flashrom/+/67535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 20 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Nov 2023 11:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in flashrom[main]: tests: Unit tests for erase function selection algo
by Anastasia Klimchuk (Code Review) 06 Nov '23

06 Nov '23

Attention is currently required from: Aarya, Anastasia Klimchuk, Edward O'Callaghan, Nikolai Artemiev, Simon Buhrow, Thomas Heijligen. Hello Aarya, Edward O'Callaghan, Simon Buhrow, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/67535?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tests: Unit tests for erase function selection algo ...................................................................... tests: Unit tests for erase function selection algo The test checks that algorithm for erase functions selection works and there are no regressions. Specifically, test contains an array of test cases. Each case initialises a given initial state of the memory for the mock chip, and layout regions on the chip, and then performs erase and write operations. At the end of operation, test asserts the following: - the state of mock chip memory is as expected, i.e. properly erased or written - erase blocks are invoked in expected order and expected number of them - chip operation (erase or write) returned 0. Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- A tests/erase_func_algo.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 753 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/67535/20 -- To view, visit https://review.coreboot.org/c/flashrom/+/67535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 20 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E
by Hsuan-ting Chen (Code Review) 06 Nov '23

06 Nov '23

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78348?usp=email ) Change subject: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/78348/comment/954ecd1d_df94ca02 : PS3, Line 15: > I also found datasheet for GD25Q127C […] I couldn't find 128C on gigadevice website, so I attached with a copy from other site. File flashchips.c: https://review.coreboot.org/c/flashrom/+/78348/comment/7a132650_1edb5ece : PS3, Line 6846: .name = "GD25Q127C/GD25Q128E", > I think this one should go before previous, alphabetically. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/78348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 Gerrit-Change-Number: 78348 Gerrit-PatchSet: 4 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 06 Nov 2023 10:40:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E
by Hsuan-ting Chen (Code Review) 06 Nov '23

06 Nov '23

Attention is currently required from: Anastasia Klimchuk, Hsuan-ting Chen, Nikolai Artemiev, Stefan Reinauer. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/78348?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Anastasia Klimchuk, Verified+1 by build bot (Jenkins) Change subject: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E ...................................................................... flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C does. So we need to split the existing GD25Q127C/GD25Q128C into two separated entries. We also introduce the new flashchip Q128E and merge it into Q127C. Datasheets: Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf Q128E and Q127C/Q128C have compatible main functions, their differences are: * Q128E uses 55 nm process, while Q127C/Q128C use 65nm * Q128E/Q127C does not support QPI * Q128E have OTP: 3072B, while Q127C/Q128C are 1536B * Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are 104MHZ So we decided to merge Q128E into Q127C. We also tested that Q128E could pass flashrom_tester while probing it as 127C/128C, so the main functionalities are compatible. Change the chip name from GD25Q127C/GD25Q128C to two entries GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate. Chip revision history: - The 'GD25Q127C/GD25Q128C' definition was added in `commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and later renamed to 'GD25Q127C/GD25Q128C' BUG=b:304863141, b:293545382 BRANCH=none TEST=flashrom_tester with flashrom binary could pass with Q128E, which contains probe, read, write, erase, and write protect Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com> Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 --- M flashchips.c M include/flashchips.h 2 files changed, 52 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/78348/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/78348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 Gerrit-Change-Number: 78348 Gerrit-PatchSet: 4 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: flashchips: Add Puya P25Q21H/11H/06H
by Anastasia Klimchuk (Code Review) 06 Nov '23

06 Nov '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58134?usp=email ) Change subject: flashchips: Add Puya P25Q21H/11H/06H ...................................................................... flashchips: Add Puya P25Q21H/11H/06H Datasheet: https://semic-boutique.com/wp-content/uploads/2016/05/P25Q21H-SSH-IT.pdf Tested P25Q21H read, write and probe with CH341a. Signed-off-by: Nita Vesa <werecatf(a)outlook.com> Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58134 Reviewed-by: Alexander Goncharov <chat(a)joursoir.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M include/flashchips.h 2 files changed, 134 insertions(+), 0 deletions(-) Approvals: Alexander Goncharov: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 9210de2..d80a574 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14130,6 +14130,135 @@ }, { + .vendor = "PUYA", + .name = "P25Q06H", + .bustype = BUS_SPI, + .manufacture_id = PUYA_ID, + .model_id = PUYA_P25Q06H, + .total_size = 64, + .page_size = 256, + /* supports SFDP */ + /* OTP: 3 x 512 bytes */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256, 256} }, + .block_erase = SPI_BLOCK_ERASE_81, + }, { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2300, 3600}, + }, + + { + .vendor = "PUYA", + .name = "P25Q11H", + .bustype = BUS_SPI, + .manufacture_id = PUYA_ID, + .model_id = PUYA_P25Q11H, + .total_size = 128, + .page_size = 256, + /* supports SFDP */ + /* OTP: 3 x 512 bytes */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256, 512} }, + .block_erase = SPI_BLOCK_ERASE_81, + }, { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2300, 3600}, + }, + + { + .vendor = "PUYA", + .name = "P25Q21H", + .bustype = BUS_SPI, + .manufacture_id = PUYA_ID, + .model_id = PUYA_P25Q21H, + .total_size = 256, + .page_size = 256, + /* supports SFDP */ + /* OTP: 3 x 512 bytes */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256, 1024} }, + .block_erase = SPI_BLOCK_ERASE_81, + }, { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2300, 3600}, + }, + + { .vendor = "SST", .name = "SST25LF020A", .bustype = BUS_SPI, diff --git a/include/flashchips.h b/include/flashchips.h index 962e65e..1150ff5 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -635,6 +635,11 @@ #define PMC_PM49FL002 0x6D #define PMC_PM49FL004 0x6E +#define PUYA_ID 0x85 +#define PUYA_P25Q06H 0x4010 +#define PUYA_P25Q11H 0x4011 +#define PUYA_P25Q21H 0x4012 + /* * The Sanyo chip found so far uses SPI, first byte is manufacturer code, * second byte is the device code, -- To view, visit https://review.coreboot.org/c/flashrom/+/58134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9 Gerrit-Change-Number: 58134 Gerrit-PatchSet: 8 Gerrit-Owner: WereCatf <werecatf(a)outlook.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

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