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Change in flashrom[staging]: Make read_ich_descriptors_from_dump() available in flashrom
by Philippe Mathieu-Daudé (Code Review) 06 Jun '17

06 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/17952 ) Change subject: Make read_ich_descriptors_from_dump() available in flashrom ...................................................................... Patch Set 14: -Code-Review (1 comment) https://review.coreboot.org/#/c/17952/14/ich_descriptors.h File ich_descriptors.h: https://review.coreboot.org/#/c/17952/14/ich_descriptors.h@68 PS14, Line 68: struct ich_desc_content { : uint32_t FLVALSIG; /* 0x00 */ : union { /* 0x04 */ : uint32_t FLMAP0; : struct { : uint32_t FCBA :8, /* Flash Component Base Address */ : NC :2, /* Number Of Components */ : :6, : FRBA :8, /* Flash Region Base Address */ : NR :3, /* Number Of Regions */ : :5; : }; : }; : union { /* 0x08 */ : uint32_t FLMAP1; : struct { : uint32_t FMBA :8, /* Flash Master Base Address */ : NM :3, /* Number Of Masters */ : :5, : FISBA :8, /* Flash ICH Strap Base Address */ : ISL :8; /* ICH Strap Length */ : }; : }; : union { /* 0x0c */ : uint32_t FLMAP2; : struct { : uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ : MSL :8, /* MCH Strap Length */ : :16; : }; : }; : }; : : struct ich_desc_component { : union { /* 0x00 */ : uint32_t FLCOMP; /* Flash Components Register */ : /* FLCOMP encoding on various generations: : * : * Chipset/Generation max_speed dual_output density : * [MHz] bits max. bits : * ICH8: 33 N/A 5 0:2, 3:5 : * ICH9: 33 N/A 5 0:2, 3:5 : * ICH10: 33 N/A 5 0:2, 3:5 : * Ibex Peak/5: 50 N/A 5 0:2, 3:5 : * Cougar Point/6: 50 30 5 0:2, 3:5 : * Patsburg: 50 30 5 0:2, 3:5 : * Panther Point/7 50 30 5 0:2, 3:5 : * Lynx Point/8: 50 30 7 0:3, 4:7 : * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? : */ : struct { : uint32_t :17, : freq_read :3, : fastread :1, : freq_fastread :3, : freq_write :3, : freq_read_id :3, : dual_output :1, /* new since Cougar Point/6 */ : :1; : } modes; : struct { : uint32_t comp1_density :3, : comp2_density :3, : :26; : } dens_old; : struct { : uint32_t comp1_density :4, /* new since Lynx Point/8 */ : comp2_density :4, : :24; : } dens_new; : }; : union { /* 0x04 */ : uint32_t FLILL; /* Flash Invalid Instructions Register */ : struct { : uint32_t invalid_instr0 :8, : invalid_instr1 :8, : invalid_instr2 :8, : invalid_instr3 :8; : }; : }; : union { /* 0x08 */ : uint32_t FLPB; /* Flash Partition Boundary Register */ : struct { : uint32_t FPBA :13, /* Flash Partition Boundary Addr */ : :19; : }; : }; : }; : : struct ich_desc_region { : union { : uint32_t FLREGs[5]; : struct { : struct { /* FLREG0 Flash Descriptor */ : uint32_t reg0_base :13, : :3, : reg0_limit :13, : :3; : }; : struct { /* FLREG1 BIOS */ : uint32_t reg1_base :13, : :3, : reg1_limit :13, : :3; : }; : struct { /* FLREG2 ME */ : uint32_t reg2_base :13, : :3, : reg2_limit :13, : :3; : }; : struct { /* FLREG3 GbE */ : uint32_t reg3_base :13, : :3, : reg3_limit :13, : :3; : }; : struct { /* FLREG4 Platform */ : uint32_t reg4_base :13, : :3, : reg4_limit :13, : :3; : }; : }; : }; : }; : : struct ich_desc_master { : union { : uint32_t FLMSTR1; : struct { : uint32_t BIOS_req_ID :16, : BIOS_descr_r :1, : BIOS_BIOS_r :1, : BIOS_ME_r :1, : BIOS_GbE_r :1, : BIOS_plat_r :1, : :3, : BIOS_descr_w :1, : BIOS_BIOS_w :1, : BIOS_ME_w :1, : BIOS_GbE_w :1, : BIOS_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR2; : struct { : uint32_t ME_req_ID :16, : ME_descr_r :1, : ME_BIOS_r :1, : ME_ME_r :1, : ME_GbE_r :1, : ME_plat_r :1, : :3, : ME_descr_w :1, : ME_BIOS_w :1, : ME_ME_w :1, : ME_GbE_w :1, : ME_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR3; : struct { : uint32_t GbE_req_ID :16, : GbE_descr_r :1, : GbE_BIOS_r :1, : GbE_ME_r :1, : GbE_GbE_r :1, : GbE_plat_r :1, : :3, : GbE_descr_w :1, : GbE_BIOS_w :1, : GbE_ME_w :1, : GbE_GbE_w :1, : GbE_plat_w :1, : :3; : }; : }; : }; : : struct ich_desc_north_strap { : union { : uint32_t STRPs[1]; /* current maximum: ich8 */ : struct { /* ich8 */ : struct { /* STRP2 (in the datasheet) */ : uint32_t MDB :1, : :31; : }; : } ich8; : }; : }; : : struct ich_desc_south_strap { : union { : uint32_t STRPs[18]; /* current maximum: cougar point */ : struct { /* ich8 */ : struct { /* STRP1 */ : uint32_t ME_DISABLE :1, : :6, : TCOMODE :1, : ASD :7, : BMCMODE :1, : :3, : GLAN_PCIE_SEL :1, : GPIO12_SEL :2, : SPICS1_LANPHYPC_SEL :1, : MESM2SEL :1, : :1, : ASD2 :7; : }; : } ich8; : struct { /* ibex peak */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss2 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : cs_ss1 :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : :8, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :20; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : cs_ss5 :1, : VE_EN :1, : :4, : MMDDE :1, : MMADDR :7, : cs_ss7 :1, : :1, : ICC_SEL :3, : MER_CL1 :1, : :10; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :8, : VE_EN2 :1, : :5, : VE_BOOT_FLASH :1, : :1, : BW_SSD :1, : NVMHCI_EN :1, : :14; : }; : struct { /* STRP15 */ : uint32_t :3, : cs_ss6 :2, : :1, : IWL_EN :1, : :1, : t209min :2, : :22; : }; : } ibex; : struct { /* cougar point */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss1 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : LINKSEC_DIS :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :4, : cs_ss2 :1, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : MESMMCTPAEN :1, : MESMMCTPA :7, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : cs_ss4 :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :2, : SUB_DECODE_EN :1, : :7, : PCHHOT_SML1ALERT_SEL :1, : :9; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : :6, : MDSMBE_EN :1, : MDSMBE_ADD :7, : :2, : ICC_SEL :3, : MER_CL1 :1, : ICC_PRO_SEL :1, : Deep_SX_EN :1, : ME_DBG_LAN :1, : :7; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :32; : }; : struct { /* STRP15 */ : uint32_t cs_ss6 :6, : IWL_EN :1, : cs_ss5 :2, : :4, : SMLINK1_THERM_SEL :1, : SLP_LAN_GP29_SEL :1, : :16; : }; : struct { /* STRP16 */ : uint32_t :32; : }; : struct { /* STRP17 */ : uint32_t ICML :1, : cs_ss7 :1, : :30; : }; : } cougar; : }; : }; : : struct ich_desc_upper_map { : union { : uint32_t FLUMAP1; /* Flash Upper Map 1 */ : struct { : uint32_t VTBA :8, /* ME VSCC Table Base Address */ : VTL :8, /* ME VSCC Table Length */ : :16; : }; : }; : struct { : union { /* JEDEC-ID Register */ : uint32_t JID; : struct { : uint32_t vid :8, /* Vendor ID */ : cid0 :8, /* Component ID 0 */ : cid1 :8, /* Component ID 1 */ : :8; : }; : }; : union { /* Vendor Specific Component Capabilities */ : uint32_t VSCC; : struct { : uint32_t ubes :2, /* Upper Block/Sector Erase Size */ : uwg :1, /* Upper Write Granularity */ : uwsr :1, /* Upper Write Status Required */ : uwews :1, /* Upper Write Enable on Write Status */ : :3, : ueo :8, /* Upper Erase Opcode */ : lbes :2, /* Lower Block/Sector Erase Size */ : lwg :1, /* Lower Write Granularity */ : lwsr :1, /* Lower Write Status Required */ : lwews :1, /* Lower Write Enable on Write Status */ : :3, : leo :16; /* Lower Erase Opcode */ : }; : }; : } vscc_table[128]; : }; > I've guarded the code using it in the next patch instead. If that's Ok, although I think an user compiling on big-endian host should be somehow warned about this. -- To view, visit https://review.coreboot.org/17952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8 Gerrit-Change-Number: 17952 Gerrit-PatchSet: 14 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:13:35 +0000 Gerrit-HasComments: Yes

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Change in flashrom[staging]: Add a convenient libflashrom interface
by Philippe Mathieu-Daudé (Code Review) 06 Jun '17

06 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/17946 ) Change subject: Add a convenient libflashrom interface ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/17946 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I00f169990830aa17b7dfae5eb74010d40c476181 Gerrit-Change-Number: 17946 Gerrit-PatchSet: 13 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:04:41 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Add functions to read/erase/write/verify by layout
by Philippe Mathieu-Daudé (Code Review) 06 Jun '17

06 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/17945 ) Change subject: Add functions to read/erase/write/verify by layout ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/17945 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ic6194cea4c4c430e0cf9d586052508a865b09c86 Gerrit-Change-Number: 17945 Gerrit-PatchSet: 12 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:03:17 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Fix linking with libpayload
by Philippe Mathieu-Daudé (Code Review) 06 Jun '17

06 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/18738 ) Change subject: Fix linking with libpayload ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/18738 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I561135209b819361d125eeaeef9ff886d6bae987 Gerrit-Change-Number: 18738 Gerrit-PatchSet: 14 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:00:25 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Make read_ich_descriptors_from_dump() available in flashrom
by Nico Huber (Code Review) 06 Jun '17

06 Jun '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/17952 ) Change subject: Make read_ich_descriptors_from_dump() available in flashrom ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/17952/14/ich_descriptors.h File ich_descriptors.h: https://review.coreboot.org/#/c/17952/14/ich_descriptors.h@68 PS14, Line 68: struct ich_desc_content { : uint32_t FLVALSIG; /* 0x00 */ : union { /* 0x04 */ : uint32_t FLMAP0; : struct { : uint32_t FCBA :8, /* Flash Component Base Address */ : NC :2, /* Number Of Components */ : :6, : FRBA :8, /* Flash Region Base Address */ : NR :3, /* Number Of Regions */ : :5; : }; : }; : union { /* 0x08 */ : uint32_t FLMAP1; : struct { : uint32_t FMBA :8, /* Flash Master Base Address */ : NM :3, /* Number Of Masters */ : :5, : FISBA :8, /* Flash ICH Strap Base Address */ : ISL :8; /* ICH Strap Length */ : }; : }; : union { /* 0x0c */ : uint32_t FLMAP2; : struct { : uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ : MSL :8, /* MCH Strap Length */ : :16; : }; : }; : }; : : struct ich_desc_component { : union { /* 0x00 */ : uint32_t FLCOMP; /* Flash Components Register */ : /* FLCOMP encoding on various generations: : * : * Chipset/Generation max_speed dual_output density : * [MHz] bits max. bits : * ICH8: 33 N/A 5 0:2, 3:5 : * ICH9: 33 N/A 5 0:2, 3:5 : * ICH10: 33 N/A 5 0:2, 3:5 : * Ibex Peak/5: 50 N/A 5 0:2, 3:5 : * Cougar Point/6: 50 30 5 0:2, 3:5 : * Patsburg: 50 30 5 0:2, 3:5 : * Panther Point/7 50 30 5 0:2, 3:5 : * Lynx Point/8: 50 30 7 0:3, 4:7 : * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? : */ : struct { : uint32_t :17, : freq_read :3, : fastread :1, : freq_fastread :3, : freq_write :3, : freq_read_id :3, : dual_output :1, /* new since Cougar Point/6 */ : :1; : } modes; : struct { : uint32_t comp1_density :3, : comp2_density :3, : :26; : } dens_old; : struct { : uint32_t comp1_density :4, /* new since Lynx Point/8 */ : comp2_density :4, : :24; : } dens_new; : }; : union { /* 0x04 */ : uint32_t FLILL; /* Flash Invalid Instructions Register */ : struct { : uint32_t invalid_instr0 :8, : invalid_instr1 :8, : invalid_instr2 :8, : invalid_instr3 :8; : }; : }; : union { /* 0x08 */ : uint32_t FLPB; /* Flash Partition Boundary Register */ : struct { : uint32_t FPBA :13, /* Flash Partition Boundary Addr */ : :19; : }; : }; : }; : : struct ich_desc_region { : union { : uint32_t FLREGs[5]; : struct { : struct { /* FLREG0 Flash Descriptor */ : uint32_t reg0_base :13, : :3, : reg0_limit :13, : :3; : }; : struct { /* FLREG1 BIOS */ : uint32_t reg1_base :13, : :3, : reg1_limit :13, : :3; : }; : struct { /* FLREG2 ME */ : uint32_t reg2_base :13, : :3, : reg2_limit :13, : :3; : }; : struct { /* FLREG3 GbE */ : uint32_t reg3_base :13, : :3, : reg3_limit :13, : :3; : }; : struct { /* FLREG4 Platform */ : uint32_t reg4_base :13, : :3, : reg4_limit :13, : :3; : }; : }; : }; : }; : : struct ich_desc_master { : union { : uint32_t FLMSTR1; : struct { : uint32_t BIOS_req_ID :16, : BIOS_descr_r :1, : BIOS_BIOS_r :1, : BIOS_ME_r :1, : BIOS_GbE_r :1, : BIOS_plat_r :1, : :3, : BIOS_descr_w :1, : BIOS_BIOS_w :1, : BIOS_ME_w :1, : BIOS_GbE_w :1, : BIOS_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR2; : struct { : uint32_t ME_req_ID :16, : ME_descr_r :1, : ME_BIOS_r :1, : ME_ME_r :1, : ME_GbE_r :1, : ME_plat_r :1, : :3, : ME_descr_w :1, : ME_BIOS_w :1, : ME_ME_w :1, : ME_GbE_w :1, : ME_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR3; : struct { : uint32_t GbE_req_ID :16, : GbE_descr_r :1, : GbE_BIOS_r :1, : GbE_ME_r :1, : GbE_GbE_r :1, : GbE_plat_r :1, : :3, : GbE_descr_w :1, : GbE_BIOS_w :1, : GbE_ME_w :1, : GbE_GbE_w :1, : GbE_plat_w :1, : :3; : }; : }; : }; : : struct ich_desc_north_strap { : union { : uint32_t STRPs[1]; /* current maximum: ich8 */ : struct { /* ich8 */ : struct { /* STRP2 (in the datasheet) */ : uint32_t MDB :1, : :31; : }; : } ich8; : }; : }; : : struct ich_desc_south_strap { : union { : uint32_t STRPs[18]; /* current maximum: cougar point */ : struct { /* ich8 */ : struct { /* STRP1 */ : uint32_t ME_DISABLE :1, : :6, : TCOMODE :1, : ASD :7, : BMCMODE :1, : :3, : GLAN_PCIE_SEL :1, : GPIO12_SEL :2, : SPICS1_LANPHYPC_SEL :1, : MESM2SEL :1, : :1, : ASD2 :7; : }; : } ich8; : struct { /* ibex peak */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss2 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : cs_ss1 :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : :8, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :20; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : cs_ss5 :1, : VE_EN :1, : :4, : MMDDE :1, : MMADDR :7, : cs_ss7 :1, : :1, : ICC_SEL :3, : MER_CL1 :1, : :10; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :8, : VE_EN2 :1, : :5, : VE_BOOT_FLASH :1, : :1, : BW_SSD :1, : NVMHCI_EN :1, : :14; : }; : struct { /* STRP15 */ : uint32_t :3, : cs_ss6 :2, : :1, : IWL_EN :1, : :1, : t209min :2, : :22; : }; : } ibex; : struct { /* cougar point */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss1 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : LINKSEC_DIS :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :4, : cs_ss2 :1, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : MESMMCTPAEN :1, : MESMMCTPA :7, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : cs_ss4 :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :2, : SUB_DECODE_EN :1, : :7, : PCHHOT_SML1ALERT_SEL :1, : :9; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : :6, : MDSMBE_EN :1, : MDSMBE_ADD :7, : :2, : ICC_SEL :3, : MER_CL1 :1, : ICC_PRO_SEL :1, : Deep_SX_EN :1, : ME_DBG_LAN :1, : :7; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :32; : }; : struct { /* STRP15 */ : uint32_t cs_ss6 :6, : IWL_EN :1, : cs_ss5 :2, : :4, : SMLINK1_THERM_SEL :1, : SLP_LAN_GP29_SEL :1, : :16; : }; : struct { /* STRP16 */ : uint32_t :32; : }; : struct { /* STRP17 */ : uint32_t ICML :1, : cs_ss7 :1, : :30; : }; : } cougar; : }; : }; : : struct ich_desc_upper_map { : union { : uint32_t FLUMAP1; /* Flash Upper Map 1 */ : struct { : uint32_t VTBA :8, /* ME VSCC Table Base Address */ : VTL :8, /* ME VSCC Table Length */ : :16; : }; : }; : struct { : union { /* JEDEC-ID Register */ : uint32_t JID; : struct { : uint32_t vid :8, /* Vendor ID */ : cid0 :8, /* Component ID 0 */ : cid1 :8, /* Component ID 1 */ : :8; : }; : }; : union { /* Vendor Specific Component Capabilities */ : uint32_t VSCC; : struct { : uint32_t ubes :2, /* Upper Block/Sector Erase Size */ : uwg :1, /* Upper Write Granularity */ : uwsr :1, /* Upper Write Status Required */ : uwews :1, /* Upper Write Enable on Write Status */ : :3, : ueo :8, /* Upper Erase Opcode */ : lbes :2, /* Lower Block/Sector Erase Size */ : lwg :1, /* Lower Write Granularity */ : lwsr :1, /* Lower Write Status Required */ : lwews :1, /* Lower Write Enable on Write Status */ : :3, : leo :16; /* Lower Erase Opcode */ : }; : }; : } vscc_table[128]; : }; > you right, this part is little-endian only (bit fields syntax). we should s I've guarded the code using it in the next patch instead. If that's not enough, we can probably use the same guard here but I usually disagree with guarded header files. -- To view, visit https://review.coreboot.org/17952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8 Gerrit-Change-Number: 17952 Gerrit-PatchSet: 14 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 12:05:11 +0000 Gerrit-HasComments: Yes

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Change in flashrom[staging]: flashchips: Add untested Winbond W25Q128.W
by Nico Huber (Code Review) 05 Jun '17

05 Jun '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/19436 ) Change subject: flashchips: Add untested Winbond W25Q128.W ...................................................................... flashchips: Add untested Winbond W25Q128.W Only difference to its sibling W25Q128.V seems to be the supply voltage. Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/19436 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M flashchips.c M flashchips.h 2 files changed, 41 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 40b6b8e..7ef361b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14825,6 +14825,46 @@ { .vendor = "Winbond", + .name = "W25Q128.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q128_W, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25X10", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 9ffb30f..28a155d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -906,7 +906,7 @@ #define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ -#define WINBOND_NEX_W25Q128_W 0x6018 /* (No W version known) W25Q128FV in QPI mode */ +#define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 -- To view, visit https://review.coreboot.org/19436 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: merged Gerrit-Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db Gerrit-Change-Number: 19436 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in flashrom[staging]: Make read_ich_descriptors_from_dump() available in flashrom
by Philippe Mathieu-Daudé (Code Review) 04 Jun '17

04 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/17952 ) Change subject: Make read_ich_descriptors_from_dump() available in flashrom ...................................................................... Patch Set 14: Code-Review-1 (1 comment) https://review.coreboot.org/#/c/17952/14/ich_descriptors.h File ich_descriptors.h: https://review.coreboot.org/#/c/17952/14/ich_descriptors.h@68 PS14, Line 68: struct ich_desc_content { : uint32_t FLVALSIG; /* 0x00 */ : union { /* 0x04 */ : uint32_t FLMAP0; : struct { : uint32_t FCBA :8, /* Flash Component Base Address */ : NC :2, /* Number Of Components */ : :6, : FRBA :8, /* Flash Region Base Address */ : NR :3, /* Number Of Regions */ : :5; : }; : }; : union { /* 0x08 */ : uint32_t FLMAP1; : struct { : uint32_t FMBA :8, /* Flash Master Base Address */ : NM :3, /* Number Of Masters */ : :5, : FISBA :8, /* Flash ICH Strap Base Address */ : ISL :8; /* ICH Strap Length */ : }; : }; : union { /* 0x0c */ : uint32_t FLMAP2; : struct { : uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ : MSL :8, /* MCH Strap Length */ : :16; : }; : }; : }; : : struct ich_desc_component { : union { /* 0x00 */ : uint32_t FLCOMP; /* Flash Components Register */ : /* FLCOMP encoding on various generations: : * : * Chipset/Generation max_speed dual_output density : * [MHz] bits max. bits : * ICH8: 33 N/A 5 0:2, 3:5 : * ICH9: 33 N/A 5 0:2, 3:5 : * ICH10: 33 N/A 5 0:2, 3:5 : * Ibex Peak/5: 50 N/A 5 0:2, 3:5 : * Cougar Point/6: 50 30 5 0:2, 3:5 : * Patsburg: 50 30 5 0:2, 3:5 : * Panther Point/7 50 30 5 0:2, 3:5 : * Lynx Point/8: 50 30 7 0:3, 4:7 : * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? : */ : struct { : uint32_t :17, : freq_read :3, : fastread :1, : freq_fastread :3, : freq_write :3, : freq_read_id :3, : dual_output :1, /* new since Cougar Point/6 */ : :1; : } modes; : struct { : uint32_t comp1_density :3, : comp2_density :3, : :26; : } dens_old; : struct { : uint32_t comp1_density :4, /* new since Lynx Point/8 */ : comp2_density :4, : :24; : } dens_new; : }; : union { /* 0x04 */ : uint32_t FLILL; /* Flash Invalid Instructions Register */ : struct { : uint32_t invalid_instr0 :8, : invalid_instr1 :8, : invalid_instr2 :8, : invalid_instr3 :8; : }; : }; : union { /* 0x08 */ : uint32_t FLPB; /* Flash Partition Boundary Register */ : struct { : uint32_t FPBA :13, /* Flash Partition Boundary Addr */ : :19; : }; : }; : }; : : struct ich_desc_region { : union { : uint32_t FLREGs[5]; : struct { : struct { /* FLREG0 Flash Descriptor */ : uint32_t reg0_base :13, : :3, : reg0_limit :13, : :3; : }; : struct { /* FLREG1 BIOS */ : uint32_t reg1_base :13, : :3, : reg1_limit :13, : :3; : }; : struct { /* FLREG2 ME */ : uint32_t reg2_base :13, : :3, : reg2_limit :13, : :3; : }; : struct { /* FLREG3 GbE */ : uint32_t reg3_base :13, : :3, : reg3_limit :13, : :3; : }; : struct { /* FLREG4 Platform */ : uint32_t reg4_base :13, : :3, : reg4_limit :13, : :3; : }; : }; : }; : }; : : struct ich_desc_master { : union { : uint32_t FLMSTR1; : struct { : uint32_t BIOS_req_ID :16, : BIOS_descr_r :1, : BIOS_BIOS_r :1, : BIOS_ME_r :1, : BIOS_GbE_r :1, : BIOS_plat_r :1, : :3, : BIOS_descr_w :1, : BIOS_BIOS_w :1, : BIOS_ME_w :1, : BIOS_GbE_w :1, : BIOS_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR2; : struct { : uint32_t ME_req_ID :16, : ME_descr_r :1, : ME_BIOS_r :1, : ME_ME_r :1, : ME_GbE_r :1, : ME_plat_r :1, : :3, : ME_descr_w :1, : ME_BIOS_w :1, : ME_ME_w :1, : ME_GbE_w :1, : ME_plat_w :1, : :3; : }; : }; : union { : uint32_t FLMSTR3; : struct { : uint32_t GbE_req_ID :16, : GbE_descr_r :1, : GbE_BIOS_r :1, : GbE_ME_r :1, : GbE_GbE_r :1, : GbE_plat_r :1, : :3, : GbE_descr_w :1, : GbE_BIOS_w :1, : GbE_ME_w :1, : GbE_GbE_w :1, : GbE_plat_w :1, : :3; : }; : }; : }; : : struct ich_desc_north_strap { : union { : uint32_t STRPs[1]; /* current maximum: ich8 */ : struct { /* ich8 */ : struct { /* STRP2 (in the datasheet) */ : uint32_t MDB :1, : :31; : }; : } ich8; : }; : }; : : struct ich_desc_south_strap { : union { : uint32_t STRPs[18]; /* current maximum: cougar point */ : struct { /* ich8 */ : struct { /* STRP1 */ : uint32_t ME_DISABLE :1, : :6, : TCOMODE :1, : ASD :7, : BMCMODE :1, : :3, : GLAN_PCIE_SEL :1, : GPIO12_SEL :2, : SPICS1_LANPHYPC_SEL :1, : MESM2SEL :1, : :1, : ASD2 :7; : }; : } ich8; : struct { /* ibex peak */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss2 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : cs_ss1 :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : :8, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :20; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : cs_ss5 :1, : VE_EN :1, : :4, : MMDDE :1, : MMADDR :7, : cs_ss7 :1, : :1, : ICC_SEL :3, : MER_CL1 :1, : :10; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :8, : VE_EN2 :1, : :5, : VE_BOOT_FLASH :1, : :1, : BW_SSD :1, : NVMHCI_EN :1, : :14; : }; : struct { /* STRP15 */ : uint32_t :3, : cs_ss6 :2, : :1, : IWL_EN :1, : :1, : t209min :2, : :22; : }; : } ibex; : struct { /* cougar point */ : struct { /* STRP0 */ : uint32_t :1, : cs_ss1 :1, : :5, : SMB_EN :1, : SML0_EN :1, : SML1_EN :1, : SML1FRQ :2, : SMB0FRQ :2, : SML0FRQ :2, : :4, : LANPHYPC_GP12_SEL :1, : LINKSEC_DIS :1, : :2, : DMI_REQID_DIS :1, : :4, : BBBS :2, : :1; : }; : struct { /* STRP1 */ : uint32_t cs_ss3 :4, : :4, : cs_ss2 :1, : :28; : }; : struct { /* STRP2 */ : uint32_t :8, : MESMASDEN :1, : MESMASDA :7, : MESMMCTPAEN :1, : MESMMCTPA :7, : MESMI2CEN :1, : MESMI2CA :7; : }; : struct { /* STRP3 */ : uint32_t :32; : }; : struct { /* STRP4 */ : uint32_t PHYCON :2, : :6, : GBEMAC_SMBUS_ADDR_EN :1, : GBEMAC_SMBUS_ADDR :7, : :1, : GBEPHY_SMBUS_ADDR :7, : :8; : }; : struct { /* STRP5 */ : uint32_t :32; : }; : struct { /* STRP6 */ : uint32_t :32; : }; : struct { /* STRP7 */ : uint32_t MESMA2UDID_VENDOR :16, : MESMA2UDID_DEVICE :16; : }; : struct { /* STRP8 */ : uint32_t :32; : }; : struct { /* STRP9 */ : uint32_t PCIEPCS1 :2, : PCIEPCS2 :2, : PCIELR1 :1, : PCIELR2 :1, : DMILR :1, : cs_ss4 :1, : PHY_PCIEPORTSEL :3, : PHY_PCIE_EN :1, : :2, : SUB_DECODE_EN :1, : :7, : PCHHOT_SML1ALERT_SEL :1, : :9; : }; : struct { /* STRP10 */ : uint32_t :1, : ME_BOOT_FLASH :1, : :6, : MDSMBE_EN :1, : MDSMBE_ADD :7, : :2, : ICC_SEL :3, : MER_CL1 :1, : ICC_PRO_SEL :1, : Deep_SX_EN :1, : ME_DBG_LAN :1, : :7; : }; : struct { /* STRP11 */ : uint32_t SML1GPAEN :1, : SML1GPA :7, : :16, : SML1I2CAEN :1, : SML1I2CA :7; : }; : struct { /* STRP12 */ : uint32_t :32; : }; : struct { /* STRP13 */ : uint32_t :32; : }; : struct { /* STRP14 */ : uint32_t :32; : }; : struct { /* STRP15 */ : uint32_t cs_ss6 :6, : IWL_EN :1, : cs_ss5 :2, : :4, : SMLINK1_THERM_SEL :1, : SLP_LAN_GP29_SEL :1, : :16; : }; : struct { /* STRP16 */ : uint32_t :32; : }; : struct { /* STRP17 */ : uint32_t ICML :1, : cs_ss7 :1, : :30; : }; : } cougar; : }; : }; : : struct ich_desc_upper_map { : union { : uint32_t FLUMAP1; /* Flash Upper Map 1 */ : struct { : uint32_t VTBA :8, /* ME VSCC Table Base Address */ : VTL :8, /* ME VSCC Table Length */ : :16; : }; : }; : struct { : union { /* JEDEC-ID Register */ : uint32_t JID; : struct { : uint32_t vid :8, /* Vendor ID */ : cid0 :8, /* Component ID 0 */ : cid1 :8, /* Component ID 1 */ : :8; : }; : }; : union { /* Vendor Specific Component Capabilities */ : uint32_t VSCC; : struct { : uint32_t ubes :2, /* Upper Block/Sector Erase Size */ : uwg :1, /* Upper Write Granularity */ : uwsr :1, /* Upper Write Status Required */ : uwews :1, /* Upper Write Enable on Write Status */ : :3, : ueo :8, /* Upper Erase Opcode */ : lbes :2, /* Lower Block/Sector Erase Size */ : lwg :1, /* Lower Write Granularity */ : lwsr :1, /* Lower Write Status Required */ : lwews :1, /* Lower Write Enable on Write Status */ : :3, : leo :16; /* Lower Erase Opcode */ : }; : }; : } vscc_table[128]; : }; you right, this part is little-endian only (bit fields syntax). we should somehow guard it restricting it to little endian, allowing same endianess flashing (i.e. armel to intel) and warning accessing cross-endian device. -- To view, visit https://review.coreboot.org/17952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8 Gerrit-Change-Number: 17952 Gerrit-PatchSet: 14 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Jun 2017 13:17:21 +0000 Gerrit-HasComments: Yes

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Change in flashrom[staging]: Enable continuous SPI reads
by Philippe Mathieu-Daudé (Code Review) 04 Jun '17

04 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/17954 ) Change subject: Enable continuous SPI reads ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/17954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Idf7aa130b1ceb3d0864bdeab5835f3341f558d41 Gerrit-Change-Number: 17954 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Jun 2017 12:47:42 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Fix linking with libpayload
by build bot (Jenkins) (Code Review) 04 Jun '17

04 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18738 ) Change subject: Fix linking with libpayload ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/351/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/352/ : SUCCESS -- To view, visit https://review.coreboot.org/18738 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I561135209b819361d125eeaeef9ff886d6bae987 Gerrit-Change-Number: 18738 Gerrit-PatchSet: 14 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:20:07 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Simple, clumsy script to test layout handling
by build bot (Jenkins) (Code Review) 04 Jun '17

04 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19352 ) Change subject: Simple, clumsy script to test layout handling ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/350/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/351/ : SUCCESS -- To view, visit https://review.coreboot.org/19352 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I37124455071bf3395384a58ad236c998f738c418 Gerrit-Change-Number: 19352 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Jun 2017 22:20:04 +0000 Gerrit-HasComments: No

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