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[S] Change in flashrom[main]: doc: Add doc for supported chipsets
by Anastasia Klimchuk (Code Review) 06 May '24

06 May '24

Attention is currently required from: Thomas Heijligen. Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82198?usp=email ) Change subject: doc: Add doc for supported chipsets ...................................................................... doc: Add doc for supported chipsets Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/supported_hw/index.rst A doc/supported_hw/supported_chipsets.rst 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/82198/1 diff --git a/doc/supported_hw/index.rst b/doc/supported_hw/index.rst index cc0f9de..18f3d26 100644 --- a/doc/supported_hw/index.rst +++ b/doc/supported_hw/index.rst @@ -8,6 +8,8 @@ supported_flashchips supported_prog/index + supported_chipsets * :doc:`supported_flashchips` * :doc:`supported_prog/index` +* :doc:`supported_chipsets` diff --git a/doc/supported_hw/supported_chipsets.rst b/doc/supported_hw/supported_chipsets.rst new file mode 100644 index 0000000..ba4de72 --- /dev/null +++ b/doc/supported_hw/supported_chipsets.rst @@ -0,0 +1,16 @@ +================== +Supported chipsets +================== + +To see the list of all supported chipsets, check the ``const struct penable chipset_enables[]`` in ``chipset_enable.c`` file in the source tree. +If you have a flashrom repo cloned locally, you can look at the file in your repo, alternatively inspect +the file `on the web UI of our GitHub mirror <https://github.com/flashrom/flashrom/blob/main/chipset_enable.c#L1768>`_. + +Each chipset entry is described by ``struct penable`` in ``include/programmer.h`` which you can inspect in the same way, either in the local source tree or +`in the GitHub web UI <https://github.com/flashrom/flashrom/blob/main/include/programmer.h#L149>`_. + +Note the ``enum test_state status`` of the chipset. ``OK`` means chipset is tested, ``NT`` means not tested, to see all possible +test states check the ``enum test_state`` definition in ``include/flash.h``. + +Also note that macros for supported buses are defined in ``chipset_enable.c`` right before ``chipset_enables[]`` array. +For example ``B_S`` means ``BUS_SPI``, check the ``chipset_enable.c`` source code for the rest of macro definitions. -- To view, visit https://review.coreboot.org/c/flashrom/+/82198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Gerrit-Change-Number: 82198 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: doc: Add doc for supported flash chips
by Anastasia Klimchuk (Code Review) 06 May '24

06 May '24

Attention is currently required from: Thomas Heijligen. Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82197?usp=email ) Change subject: doc: Add doc for supported flash chips ...................................................................... doc: Add doc for supported flash chips Change-Id: I05fb60a4caf2cfb30586fa482687b10638996395 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/supported_hw/index.rst A doc/supported_hw/supported_flashchips.rst 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/82197/1 diff --git a/doc/supported_hw/index.rst b/doc/supported_hw/index.rst index 5b3305c..cc0f9de 100644 --- a/doc/supported_hw/index.rst +++ b/doc/supported_hw/index.rst @@ -6,6 +6,8 @@ :maxdepth: 3 :hidden: + supported_flashchips supported_prog/index +* :doc:`supported_flashchips` * :doc:`supported_prog/index` diff --git a/doc/supported_hw/supported_flashchips.rst b/doc/supported_hw/supported_flashchips.rst new file mode 100644 index 0000000..d7128e0 --- /dev/null +++ b/doc/supported_hw/supported_flashchips.rst @@ -0,0 +1,20 @@ +===================== +Supported flash chips +===================== + +The list of all supported flash chips is in ``flashchips.c`` file in the source tree. +If you have a flashrom repo cloned locally, you can look at the file in your repo, +alternatively inspect the file on the `web UI of our GitHub mirror <https://github.com/flashrom/flashrom/blob/main/flashchips.c>`_. + +If you want to check whether a flash chip is supported in the given release, you can rebase your local +repo at the release tag, alternatively select a tag/branch in GitHub web UI (dropdown on the top-left). + +Each chip definition is described by a ``struct flashchip`` in ``include/flash.h``, which you can inspect in the same way, +either in local source tree or on GitHub web UI. + +Note the ``.tested`` status of the chip. If the status is ``TEST_UNTESTED`` this means chip definition has been added purely based on +datasheet, but without testing on real hardware. + +Instructions how to update tested status of the chip are here: :doc:`/contrib_howtos/how_to_mark_chip_tested`. + +Instructions how to add support for a chip are here: :doc:`/contrib_howtos/how_to_add_new_chip`. -- To view, visit https://review.coreboot.org/c/flashrom/+/82197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I05fb60a4caf2cfb30586fa482687b10638996395 Gerrit-Change-Number: 82197 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: doc: Fix index files in Supported HW section
by Anastasia Klimchuk (Code Review) 06 May '24

06 May '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82196?usp=email ) Change subject: doc: Fix index files in Supported HW section ...................................................................... doc: Fix index files in Supported HW section By default toctree in the index file displays full tree of docs with all the nested levels, and it's too much detail. Besides, left side menu displays the tree anyway, so duplication is not needed. Supported hardware section has the deepest nesting out of all other docs. This patch changes high-level index files to only display flat list of next level subtree. On deeper level, full index is displayed. Change-Id: Ia15e9766cce6f19be1e69fbb1236a327ae3d57b3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/supported_hw/index.rst M doc/supported_hw/supported_prog/index.rst 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/82196/1 diff --git a/doc/supported_hw/index.rst b/doc/supported_hw/index.rst index 5552326..5b3305c 100644 --- a/doc/supported_hw/index.rst +++ b/doc/supported_hw/index.rst @@ -4,5 +4,8 @@ .. toctree:: :maxdepth: 3 + :hidden: supported_prog/index + +* :doc:`supported_prog/index` diff --git a/doc/supported_hw/supported_prog/index.rst b/doc/supported_hw/supported_prog/index.rst index 9d71578..1dfabd5 100644 --- a/doc/supported_hw/supported_prog/index.rst +++ b/doc/supported_hw/supported_prog/index.rst @@ -3,5 +3,13 @@ .. toctree:: :maxdepth: 2 + :hidden: serprog/index + +flashrom supports many different programmers, for the full list you can look into `programmer_table.c <https://github.com/flashrom/flashrom/blob/main/programmer_table.c>`_ +in the source tree. Some of the programmers have their own documentation pages, see below. + +Patches to add/update documentation, or migrate docs from `old wiki website <https://wiki.flashrom.org/Supported_programmers>`_ are very much appreciated. + +* :doc:`serprog/index` -- To view, visit https://review.coreboot.org/c/flashrom/+/82196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ia15e9766cce6f19be1e69fbb1236a327ae3d57b3 Gerrit-Change-Number: 82196 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in flashrom[main]: doc: Convert serprog docs to rst and add to doc directory
by Anastasia Klimchuk (Code Review) 06 May '24

06 May '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82018?usp=email ) Change subject: doc: Convert serprog docs to rst and add to doc directory ...................................................................... doc: Convert serprog docs to rst and add to doc directory Change-Id: Ie52f1e051ed215d61d5fb535e3eddeac71f64d13 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82018 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sydney <git(a)funkeleinhorn.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- D Documentation/serprog-protocol.txt M doc/classic_cli_manpage.rst M doc/index.rst A doc/supported_hw/index.rst A doc/supported_hw/supported_prog/index.rst A doc/supported_hw/supported_prog/serprog/166px-Serprogduino_v2.jpeg A doc/supported_hw/supported_prog/serprog/250px-Arduino_5V_lpc_spi_shield.jpg A doc/supported_hw/supported_prog/serprog/250px-Arduino_lpcspi_shield_render.png A doc/supported_hw/supported_prog/serprog/300px-AtmegaXXu2-flasher.jpg A doc/supported_hw/supported_prog/serprog/300px-Avr_rs232_programmer.jpg A doc/supported_hw/supported_prog/serprog/300px-HydraFW_Default_PinAssignment.png A doc/supported_hw/supported_prog/serprog/300px-Serprog_0001.jpeg A doc/supported_hw/supported_prog/serprog/300px-Teensy31_lpcspi_flasher.jpg A doc/supported_hw/supported_prog/serprog/P1v1_arduino328.png A doc/supported_hw/supported_prog/serprog/P1v2_arduino1280.png A doc/supported_hw/supported_prog/serprog/P2v1_resdivider.png A doc/supported_hw/supported_prog/serprog/P2v2_oc_cs.png A doc/supported_hw/supported_prog/serprog/P2v3_buffer4050.png A doc/supported_hw/supported_prog/serprog/P3v1_dil8_so8_spi.png A doc/supported_hw/supported_prog/serprog/P3v2_so16_spi.png A doc/supported_hw/supported_prog/serprog/arduino_flasher.rst A doc/supported_hw/supported_prog/serprog/arduino_flasher_3.3v.rst A doc/supported_hw/supported_prog/serprog/index.rst A doc/supported_hw/supported_prog/serprog/overview.rst A doc/supported_hw/supported_prog/serprog/serprog-protocol.rst A doc/supported_hw/supported_prog/serprog/teensy_3_1.rst 26 files changed, 806 insertions(+), 124 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Sydney: Looks good to me, but someone else must approve diff --git a/Documentation/serprog-protocol.txt b/Documentation/serprog-protocol.txt deleted file mode 100644 index d001ceb..0000000 --- a/Documentation/serprog-protocol.txt +++ /dev/null @@ -1,123 +0,0 @@ -Serial Flasher Protocol Specification - version 1 (0x01 return value == 1) - -Command And Answer Sequence - all commands give an answer. -PC: COMMAND(8bit) <parameters determined by opcode> -DEV: ACK/NAK(8bit) <OPTIONAL RETURN BYTES (only if ACK)> / nothing -Command 0x10 (SYNCNOP) has a special return of NAK+ACK for synchronization. - -ACK = 0x06 -NAK = 0x15 - -All multibyte values are little-endian. Addresses and lengths are 24-bit. - -COMMAND Description Parameters Return Value -0x00 NOP none ACK -0x01 Query programmer iface version none ACK + 16bit version (nonzero) -0x02 Query supported commands bitmap none ACK + 32 bytes (256 bits) of supported cmds flags -0x03 Query programmer name none ACK + 16 bytes string (null padding) / NAK -0x04 Query serial buffer size none ACK + 16bit size / NAK -0x05 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK -0x06 Query connected address lines none ACK + 8bit line count / NAK -0x07 Query operation buffer size none ACK + 16bit size / NAK -0x08 Query maximum write-n length none ACK + 24bit length (0==2^24) / NAK -0x09 Read byte 24-bit addr ACK + BYTE / NAK -0x0A Read n bytes 24-bit addr + 24-bit length ACK + length bytes / NAK -0x0B Initialize operation buffer none ACK / NAK -0x0C Write to opbuf: Write byte 24-bit addr + 8-bit byte ACK / NAK (NOTE: takes 5 bytes in opbuf) -0x0D Write to opbuf: Write n 24-bit length + 24-bit addr + ACK / NAK (NOTE: takes 7+n bytes in opbuf) - + length bytes of data -0x0E Write to opbuf: delay 32-bit usecs ACK / NAK (NOTE: takes 5 bytes in opbuf) -0x0F Execute operation buffer none ACK / NAK -0x10 Sync NOP none NAK + ACK (for synchronization) -0x11 Query maximum read-n length none ACK + 24-bit length (0==2^24) / NAK -0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK -0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK - + slen bytes of data -0x14 Set SPI clock frequency in Hz 32-bit requested frequency ACK + 32-bit set frequency / NAK -0x15 Toggle flash chip pin drivers 8-bit (0 disable, else enable) ACK / NAK -0x16 Set SPI Chip Select 8-bit ACK / NAK -0x17 Set SPI Mode 8-bit ACK / NAK -0x18 Set CS Mode 8-bit ACK / NAK -0x?? unimplemented command - invalid. - - -Additional information of the above commands: - About unimplemented commands / startup sequence: - Only commands allowed to be used without checking anything are 0x00,0x10 and 0x01 (NOP,SYNCNOP,Q_IFACE). - If 0x01 doesn't return 1, dont do anything if you dont support a newer protocol. - Then, check support for any other opcode (except 0x02) by using 0x02 (Q_CMDMAP). - 0x02 (Q_CMDMAP): - The map's bits are mapped as follows: - cmd 0 support: byte 0 bit 0 - cmd 1 support: byte 0 bit 1 - cmd 7 support: byte 0 bit 7 - cmd 8 support: byte 1 bit 0, and so on. - 0x04 (Q_SERBUF): - If the programmer has a guaranteed working flow control, - it should return a big bogus value - eg 0xFFFF. - 0x05 (Q_BUSTYPE): - The bit's are defined as follows: - bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI. - 0x06 (Q_CHIPSIZE): - Only applicable to parallel programmers. - An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap. - 0x08 (Q_WRNMAXLEN): - If a programmer reports a bigger maximum write-n length than the serial buffer size, - it is assumed that the programmer can process the data fast enough to take in the - reported maximum write-n without problems. - 0x0F (O_EXEC): - Execute operation buffer will also clear it, regardless of the return value. - 0x11 (Q_RDNMAXLEN): - If this command is not supported, assume return of 0 (2^24). - 0x12 (S_BUSTYPE): - Set's the used bustype if the programmer can support more than one flash protocol. - Sending a byte with more than 1 bit set will make the programmer decide among them - on it's own. Bit values as with Q_BUSTYPE. - 0x13 (O_SPIOP): - Send and receive bytes via SPI. - Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used - to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. - This operation is immediate, meaning it doesn't use the operation buffer. - 0x14 (S_SPI_FREQ): - Set the SPI clock frequency. The 32-bit value indicates the - requested frequency in Hertz. Value 0 is reserved and should - be NAKed by the programmer. The requested frequency should be - mapped by the programmer software to a supported frequency - lower than the one requested. If there is no lower frequency - available the lowest possible should be used. The value - chosen is sent back in the reply with an ACK. - 0x15 (S_PIN_STATE): - Sets the state of the pin drivers connected to the flash chip. Disabling them allows other - devices (e.g. a mainboard's chipset) to access the chip. This way the serprog controller can - remain attached to the flash chip even when the board is running. The user is responsible to - NOT connect VCC and other permanently externally driven signals to the programmer as needed. - If the value is 0, then the drivers should be disabled, otherwise they should be enabled. - 0x16 (S_SPI_CS): - Set which SPI Chip Select pin to use. This operation is immediate, - meaning it doesn't use the operation buffer. - 0x17 (S_SPI_MODE): - Set which SPI Mode to use for 0x13 O_SPIOP commands. - This operation is immediate, meaning it doesn't use the operation buffer. - The current defined modes are: - 0x00: SPI Half Duplex (default) - 0x01: SPI Full Duplex - 0x18 (S_CS_MODE): - Set which CS Mode to use. The CS Mode determines the CS behaviour. - This allows manual control over the CS. - This operation is immediate, meaning it doesn't use the operation buffer. - The current defined modes are: - 0x00: CS Auto Mode. The CS gets selected before 0x13 O_SPIOP commands and - deselected afterwards. (default) - 0x01: CS Selected. The CS will be selected until another mode is set. - 0x02: CS Deselected. The CS will be deselected until another mode is set. - About mandatory commands: - The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, - but one can't really do anything with these commands. - Support for the following commands is necessary for flashrom to operate properly: - S_CMD_Q_SERBUF, S_CMD_Q_OPBUF, S_CMD_Q_WRNMAXLEN, S_CMD_R_BYTE, - S_CMD_R_NBYTES, S_CMD_O_INIT, S_CMD_O_WRITEB, S_CMD_O_WRITEN, - S_CMD_O_DELAY, S_CMD_O_EXEC. - In addition, support for these commands is recommended: - S_CMD_Q_PGMNAME, S_CMD_Q_BUSTYPE, S_CMD_Q_CHIPSIZE (if parallel). - -See also serprog.c diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst index f40d19e..beafd82 100644 --- a/doc/classic_cli_manpage.rst +++ b/doc/classic_cli_manpage.rst @@ -749,7 +749,7 @@ The particular programmer implementation needs to support this feature, for it to work. If the requested chip select isn't available, flashrom will fail safely. -More information about serprog is available in **serprog-protocol.txt** in the source distribution. +More information about serprog is available in this document: :doc:`/supported_hw/supported_prog/serprog/serprog-protocol`. buspirate_spi programmer diff --git a/doc/index.rst b/doc/index.rst index 60c42b0..f32f182 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -12,6 +12,7 @@ dev_guide/index user_docs/index contrib_howtos/index + supported_hw/index classic_cli_manpage contact release_notes/index diff --git a/doc/supported_hw/index.rst b/doc/supported_hw/index.rst new file mode 100644 index 0000000..5552326 --- /dev/null +++ b/doc/supported_hw/index.rst @@ -0,0 +1,8 @@ +================== +Supported hardware +================== + +.. toctree:: + :maxdepth: 3 + + supported_prog/index diff --git a/doc/supported_hw/supported_prog/index.rst b/doc/supported_hw/supported_prog/index.rst new file mode 100644 index 0000000..9d71578 --- /dev/null +++ b/doc/supported_hw/supported_prog/index.rst @@ -0,0 +1,7 @@ +Supported programmers +===================== + +.. toctree:: + :maxdepth: 2 + + serprog/index diff --git a/doc/supported_hw/supported_prog/serprog/166px-Serprogduino_v2.jpeg b/doc/supported_hw/supported_prog/serprog/166px-Serprogduino_v2.jpeg new file mode 100644 index 0000000..ffe8558 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/166px-Serprogduino_v2.jpeg Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/250px-Arduino_5V_lpc_spi_shield.jpg b/doc/supported_hw/supported_prog/serprog/250px-Arduino_5V_lpc_spi_shield.jpg new file mode 100644 index 0000000..1886e26 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/250px-Arduino_5V_lpc_spi_shield.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/250px-Arduino_lpcspi_shield_render.png b/doc/supported_hw/supported_prog/serprog/250px-Arduino_lpcspi_shield_render.png new file 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/dev/null +++ b/doc/supported_hw/supported_prog/serprog/300px-HydraFW_Default_PinAssignment.png Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/300px-Serprog_0001.jpeg b/doc/supported_hw/supported_prog/serprog/300px-Serprog_0001.jpeg new file mode 100644 index 0000000..af1bcaf --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/300px-Serprog_0001.jpeg Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/300px-Teensy31_lpcspi_flasher.jpg b/doc/supported_hw/supported_prog/serprog/300px-Teensy31_lpcspi_flasher.jpg new file mode 100644 index 0000000..9289aae --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/300px-Teensy31_lpcspi_flasher.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/P1v1_arduino328.png b/doc/supported_hw/supported_prog/serprog/P1v1_arduino328.png new file mode 100644 index 0000000..0fd808b --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/P1v1_arduino328.png Binary files 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0000000..d2ebd8c --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/P2v3_buffer4050.png Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/P3v1_dil8_so8_spi.png b/doc/supported_hw/supported_prog/serprog/P3v1_dil8_so8_spi.png new file mode 100644 index 0000000..3a2f134 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/P3v1_dil8_so8_spi.png Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/P3v2_so16_spi.png b/doc/supported_hw/supported_prog/serprog/P3v2_so16_spi.png new file mode 100644 index 0000000..7ae1379 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/P3v2_so16_spi.png Binary files differ diff --git a/doc/supported_hw/supported_prog/serprog/arduino_flasher.rst b/doc/supported_hw/supported_prog/serprog/arduino_flasher.rst new file mode 100644 index 0000000..ada0519 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/arduino_flasher.rst @@ -0,0 +1,227 @@ +=============== +Arduino flasher +=============== + +.. container:: danger, admonition + + **WARNING** + + Make sure that the Arduino SPI voltages and the flash chip voltages matches: Without any extra resistors or level shifter, + the Arduino Uno and Duemillanove SPI pins are at 5V, while most chips operate at 3.3v. + +Hardware basics +=============== + +You'll need to have: + +* a supported Arduino, these are + + * any based on the ATmega328 (/168/88 will work with small changes too), like the Arduino Uno R3. + * Arduino Mega or Mega2560, but notice that the software has a different branch for them. + +* a way to convert the 5V logic levels to 3.3V (except if 3.3V arduino, these are rarer) +* a 3.3V SPI flash chip that is supported by flashrom + +Notes: + +* The FTDI based usb-serial converters are the fastest. +* 1.8V conversion isnt covered here, yet. + +There are some simple schematics included here (`source <https://github.com/flashrom/wiki-arduino-spi-example-schematics>`_). +The idea is that you pick one version from each part 1 through 3, and connect the pin/net names. + +Part 1: The Arduino +------------------- + +ATmega328 based ones: + +.. image:: P1v1_arduino328.png + +For the Arduino Megas: + +.. image:: P1v2_arduino1280.png + +Part 2: Level translation +------------------------- + +There are a few options here, ranging from the simple resistors (v1) to a buffer chip (v3). + +One thing to remember about the resistor dividers is that they're not strong enough to do ISP. + +Here's the simple resistors: + +.. image:: P2v1_resdivider.png + +The part count for the resistor divider is 6 resistors of 2 types or 9 of one type. + +Here's one with 5 resistors, the downside is that you'll need to modify the firmware a little: + +.. image:: P2v2_oc_cs.png + +The 3rd version is using the DIP16 HEF4050 buffer chip: + +.. image:: P2v3_buffer4050.png + +Part 3: The SPI Flash chip +-------------------------- + +The DIL-8 and SOIC-8 versions connect like this: + +.. image:: P3v1_dil8_so8_spi.png + +For the SMD SOIC-16 chips the pinout is: + +.. image:: P3v2_so16_spi.png + +Gallery of some flashers +======================== + +.. image:: 166px-Serprogduino_v2.jpeg + +.. _arduino shield: + +Alternative: Shield with SPI and LPC/FWH for 5V Arduinos +======================================================== + +.. image:: 250px-Arduino_5V_lpc_spi_shield.jpg + +.. image:: 250px-Arduino_lpcspi_shield_render.png + +`Firmware and hardware sources <https://github.com/urjaman/frser-m328lpcspi>`_ + +`Shield PCB shared at oshpark <https://oshpark.com/shared_projects/E6jwmbWy>`_ + +* This shield and firmware was built for 5V ATMega328s with FTDI, variations to that will need adaptations in building the shield and/or in the firmware. + The Uno R3 will work with the fast-usbserial U2 firmware. +* This shield uses a different pin for SPI CS than the other circuits on this page, and has LPC/FWH capability, thus different firmware. + Frser-duino does have the code for using the CS like in this shield, but you need to modify spihw.h. +* Note: do check for any incompatibilities between your arduino and the shield, eg. the PD7 used as LPC CLK clashes with BT reset in BT arduinos. +* For LPC/FWH, current (16/02/01) flashrom trunk will be really slow, please use this branch instead. + +Software and setup +================== + +The Arduino Uno R3 and other arduinos with an ATmega8U2/16U2 as an usb-serial converter have lots of bugs in their usb-serial firmware +that prevent it from operating at more than a limited 115200 baud. The frser-duino firmware works around this by default if you use the appropriate make target, +but there exists a firmware that allows these to be used like the FTDI at 2Mbaud: `fast-usbserial <https://github.com/urjaman/fast-usbserial>`_. + +Setup +----- + +Required software +^^^^^^^^^^^^^^^^^ + +To make it work you need: + +* A recent flashrom with the serprog protocol compiled in (most packaged versions do) +* `frser-duino which runs on the arduino <https://github.com/urjaman/frser-duino>`_ + + * This page used to link to `serprog-duino <https://gitorious.org/gnutoo-personal-arduino-projects/serprog-duino>`_, + frser-duino should build in a similar fashion and has better serial buffering and some other features (spi speed setting). + +* The avr toolchain(avr-gcc, avr-libc,make etc...) + +Building the software +^^^^^^^^^^^^^^^^^^^^^ + +First get the firmware source:: + + $ git clone --recursive git://github.com/urjaman/frser-duino + $ cd frser-duino + +Then build it: + +For a board with a 8u2 or a 16u2:: + + $ make u2 && make flash-u2 + +For a board with an ftdi:: + + $ make ftdi && make flash-ftdi + +Building for the Mega1280 or 2560 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +As above, except use the branch for the 1280:: + + $ git clone --recursive git://github.com/urjaman/frser-duino -b arduino-mega-1280 + +For the Mega2560, change the Makefile to target the correct MCU (replace 1280 with 2560). Please also verify that the avrdude command is as expected for your device. + +Running flashrom +^^^^^^^^^^^^^^^^ + +The right flashrom arguments are explained in the :doc:`/classic_cli_manpage`, or here. + +Available targets: + +* ftdi, flash-ftdi: + For the Arduinos with an FTDI + compatible flashrom arguments:: + + flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + + Other boards using an hardware USB<->Serial converter might work too. + +* u2, flash-u2: + For the Arduino with a 8u2 or a 16u2 + compatible flashrom arguments:: + + flashrom -p serprog:dev=/dev/ttyACM0:115200 + +So for a board that has an ftdi that would give:: + + flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + +Speed +^^^^^ + +The speed is very dependant on the flash chip used: + +* Its capacity impacts the speed a lot, as you would expect. +* The chip model as also a huge impact. + +Duemillanove +^^^^^^^^^^^^ + +With the duemillanove:: + + # time flashrom -p serprog:dev=/dev/ttyUSB0:2000000 -r duemillanove.rom + flashrom v0.9.7-r1711 on Linux 3.18.3-gnu-1 (i686) + flashrom is free software, get the source code at http://www.flashrom.org + + Calibrating delay loop... delay loop is unreliable, trying to continue OK. + serprog: Programmer name is "serprog-duino" + Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on serprog. + Reading flash... done. + flashrom -p serprog:dev=/dev/ttyUSB0:2000000 -r duemillanove.rom + +we have:: + + 4.23s user 0.29s system 8% cpu 56.010 total + +Uno +^^^ + +With the Arduino uno:: + + # flashrom -p serprog:dev=/dev/ttyACM0:115200 -r uno.rom + flashrom v0.9.7-r1711 on Linux 3.18.3-gnu-1 (i686) + flashrom is free software, get the source code at http://www.flashrom.org + + Calibrating delay loop... delay loop is unreliable, trying to continue OK. + serprog: Programmer name is "serprog-duino" + Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on serprog. + Reading flash... done. + flashrom -p serprog:dev=/dev/ttyACM0:115200 -r uno.rom + +we have:: + + 4.77s user 0.65s system 1% cpu 6:02.43 total + +Tested chips +^^^^^^^^^^^^ + +* SST25VF016B => huge issues, not recognized by the 3.3v version, had to use the 5v version which is over maximum allowed voltage, + also had to lower the serial speed to 115200, ultra slow to write(seem related to the chip itself, since that with the openmoko programmer it's even slower...)... +* W25X80 works well in 3.3v mode(5v works also but it's highly not advised to use 5v) diff --git a/doc/supported_hw/supported_prog/serprog/arduino_flasher_3.3v.rst b/doc/supported_hw/supported_prog/serprog/arduino_flasher_3.3v.rst new file mode 100644 index 0000000..0f4b76c --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/arduino_flasher_3.3v.rst @@ -0,0 +1,237 @@ +==================== +Arduino flasher 3.3v +==================== + +Introduction +============ + +This explains how to: + +* Easily lower the voltage of an arduino +* Use that arduino to flash a coreboot image on a GM45 Thinkpad with a SOIC16 chip + +It requires: + +* An AVR Arduino at 5v +* An USB<->Serial adapter capable of providing enough current to power up: + + * The arduino + * The flash chip + * The circuits around the flash chip + +It was tested with: + +* An Arduino.org "nano version 3.3" +* A Sparkfun "FTDI Basic 3v3" (Uses an FTDI FT232R) + +Caveats and warnings: + +* It requires you to to never connect an USB cable between the Arduino USB port and the computer while the flasher is connected to a flash chip. + This would result in the I/O voltage being 5V instead of 3.3V. If you think you may accidentally connect it this way, this flasher isn't the right solution for you. +* You need to read the tutorial, if you don't understand it, it's probably not for you. In doubt you could ask for some help in flashrom real-time channels + or on the mailing list, see :doc:`/contact`. +* For now it requires to patch frser-duino + +Theory +======== + +In the `Atmega328/P datasheet <https://web.archive.org/web/20181004225154/ww1.microchip.com/downloads/en/D…>`_, +the "32.3. Speed Grades" chapter describes (pages 368 and 369) the link between maximum frequency of the microcontroller and the voltage. At 3.3v, the maximum frequency is 12Mhz. + +HOWTO +======== + +Build the code installing it on the arduino +------------------------------------------- + +Building frser-duino +^^^^^^^^^^^^^^^^^^^^ + +First download frser-duino:: + + $ git clone --recursive https://github.com/urjaman/frser-duino.git + $ cd frser-duino + +Then modify the ``F_CPU`` value in ``main.h`` to be 12Mhz instead of 16Mhz. ``F_CPU`` will look like that:: + + #define F_CPU 16000000UL + +Change it to:: + + #define F_CPU 12000000UL + +You can then build the code:: + + $ make ftdi + +Installing the code on the arduino +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Before installing the code on arduino we want to make sure that we are talking to the right device. +To do that make sure that the arduino is not connected to your computer and run:: + + $ ls -l /dev/ttyUSB0 + +If everything went fine it will output something like that:: + + ls: cannot access '/dev/ttyUSB0': No such file or directory + +If instead it looks like that:: + + crw-rw---- 1 root uucp 188, 0 27 févr. 14:30 /dev/ttyUSB0 + +then something else is connected to your computer at ``/dev/ttyUSB0``. If you can't figure what's going on by yourself, +it's better to try get help on the flashrom channels to fix the issue, see :doc:`/contact`. + +Then connect your arduino to the computer and run the same command:: + + $ ls -l /dev/ttyUSB0 + +This time it's supposed to output a line that looks more or less like that:: + + crw-rw---- 1 root uucp 188, 0 27 févr. 14:30 /dev/ttyUSB0 + +At this point we're pretty confident that ``/dev/ttyUSB0`` corresponds to the arduino, so we can install the code with:: + + $ make flash-ftdi + +Once it is installed we can now test that everything went fine with:: + + $ flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + +This will make flashrom talk to the arduino to verify if everything is fine up to this point. + +If everything went fine it will look more or less like that:: + + $ flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + /sys/firmware/dmi/tables/smbios_entry_point: Permission denied + /dev/mem: Permission denied + /sys/firmware/dmi/tables/smbios_entry_point: Permission denied + /dev/mem: Permission denied + flashrom v1.0 on Linux 4.15.2-gnu-1 (i686) + flashrom is free software, get the source code at https://flashrom.org + + Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). + serprog: Programmer name is "frser-duino" + serprog: requested mapping AT45CS1282 is incompatible: 0x1080000 bytes at 0xfef80000. + No EEPROM/flash device found. + Note: flashrom can never write if the flash chip isn't found automatically. + +This is the important line:: + + serprog: Programmer name is "frser-duino" + +It means that flashrom is able to talk to the flasher, which reports itself as "frser-duino" We also have the following line:: + + No EEPROM/flash device found. + +which tells that it didn't find any flash. This is what's supposed to happen since we didn't connect any yet. + +Build the programmer +-------------------- + +Connect the programmer to the USB<->Serial adapter +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To do that: + +* Connect the FTDI adapter RX to the TX of the arduino +* Connect the FTDI adapter TX to the RX of the arduino +* Connect the 3V3 of the FTDI adapter to the 5V pin of the Arduino +* Connect the GND of the FTDI adapter to the GDN of the arduino. + +Here's a summary of the above: + +======== ========================= +Arduino USB<->Serial port adapter +======== ========================= +RX TX +TX RX +5v 3.3v +GND GND +======== ========================= + +You can now check that the programmer is responding with:: + + flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + +Since you didn't connect yet a flash chip, it will says it found no flash chips:: + + $ flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + /sys/firmware/dmi/tables/smbios_entry_point: Permission denied + /dev/mem: Permission denied + /sys/firmware/dmi/tables/smbios_entry_point: Permission denied + /dev/mem: Permission denied + flashrom v1.0 on Linux 4.15.2-gnu-1 (i686) + flashrom is free software, get the source code at https://flashrom.org + + Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). + serprog: Programmer name is "frser-duino" + serprog: requested mapping AT45CS1282 is incompatible: 0x1080000 bytes at 0xfef80000. + No EEPROM/flash device found. + Note: flashrom can never write if the flash chip isn't found automatically. + +Again like before the important parts are:: + + serprog: Programmer name is "frser-duino" + +And:: + + No EEPROM/flash device found. + +If you made it up to this point, you successfully built the flasher. + +Using the programmer +-------------------- + +Connect the programmer to a flash chip +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Since the flasher has been built, you probably want to use it. + +If you use a clip (Like a SOIC-8 or SOIC16 Pomona clip), connect it to the Arduino +Connect the chip to the clip, or if you don't use a clip, the chip to the Arduino +Here's how to connect the flash chips to the programmer: + +=========== ========================== =================== ===================== +Arduino pin Function Flash chip pin name SOIC16 Flash chip pin +=========== ========================== =================== ===================== +D13 CLK (Clock) CLK 16 +D12 MISO (Master In Slave Out) MISO or SO 8 +D11 MOSI (Master Out Slave In) MOSI or SI 15 +D10 CS# (Chip Select) CS# or CS OR SS 7 +GND GND (Ground) GND 10 +5V 3.3V VCC 2 +5V 3.3V WP# (Write Protect) 9 +5V 3.3V HOLD# 1 +=========== ========================== =================== ===================== + +Then connect an USB cable between the USB<->Serial adapter and the computer. +Never connect the cable between the Arduino USB port and the computer while the flasher is connected to a flash chip. +That would result in the I/O voltage being 5V instead of 3.3V. + +Flashing +^^^^^^^^ + +Run flashrom like that:: + + flashrom -p serprog:dev=/dev/ttyUSB0:2000000 + +With some models of Macronix flash chip (that are present in the Thinkpad X200) you might need to add ``spispeed=100k`` like that:: + + flashrom -p serprog:dev=/dev/ttyUSB0:2000000,spispeed=100k + +Thanks +======== + +Thanks a lot to SwiftGeek on IRC (#libreboot on Libera) for finding the first workaround to make it detect flash chips at lower voltage. +Thanks also for telling me about the Macronix issues on the Thinkpad X200. This project would not have been possible without that. + +Page license +============ + +This page is available under the following licenses: + +* `CC-BY-SA 3.0 <https://creativecommons.org/licenses/by-sa/3.0/legalcode>`_ +* `CC-BY-SA 4.0 <https://creativecommons.org/licenses/by-sa/4.0/legalcode>`_ or later +* `GFDL 1.3 <https://www.gnu.org/licenses/fdl-1.3.txt>`_ or later diff --git a/doc/supported_hw/supported_prog/serprog/index.rst b/doc/supported_hw/supported_prog/serprog/index.rst new file mode 100644 index 0000000..c1c2d73 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/index.rst @@ -0,0 +1,11 @@ +Serprog +======== + +.. toctree:: + :maxdepth: 1 + + overview + serprog-protocol + arduino_flasher_3.3v + arduino_flasher + teensy_3_1 diff --git a/doc/supported_hw/supported_prog/serprog/overview.rst b/doc/supported_hw/supported_prog/serprog/overview.rst new file mode 100644 index 0000000..b274b99 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/overview.rst @@ -0,0 +1,83 @@ +================== +Serprog (overview) +================== + +This page collects information about the serprog protocol and the programmers implementing it. + +Protocol +======== + +See :doc:`/supported_hw/supported_prog/serprog/serprog-protocol`. It is designed to be compact and allow efficient storage in limited memory of programmer devices. + +AVR flasher by Urja Rannikko +============================ + +.. image:: 300px-Avr_rs232_programmer.jpg + +The Prototype RS232 AVR parallel flash programmer of Urja Rannikko was the first implementation of the serprog protocol. + +The source code can be found `here <https://github.com/urjaman/frser-atmega88>`_. + +InSystemFlasher by Juhana Helovuo +================================= + +This was the first one that talks to SPI devices via serial over USB. +Details can be found in the `coreboot wiki <https://www.coreboot.org/InSystemFlasher>`_ and in this +`coreboot mailing list thread <https://mail.coreboot.org/pipermail/coreboot/2011-February/063349.html>`_. + +atmegaXXu2-flasher by Stefan Tauner +=================================== + +Like the InSystemFlasher this one uses LUFA on an AVR microcontroller to tunnel the serial data over USB. + +.. image:: 300px-AtmegaXXu2-flasher.jpg + +Various Arduino based flashers +============================== + +Frser-duino +----------- + +This project contains `source code <https://github.com/urjaman/frser-duino/>`_ to install on Arduino devices. + +This developer also have various ports on `github repo <https://github.com/urjaman?tab=repositories>`_ for several microcontroller boards, such as: + +* `frser-teensyflash <https://github.com/urjaman/frser-teensyflash>`_: A port for the teensy microcontroller board + +There also various other interesting projects such as: + +* `fast-usbserial <https://github.com/urjaman/fast-usbserial>`_: A software to make arduino with 8u2 or 16u2 flashing faster and more reliable] +* :ref:`arduino shield` + +Using a 5v Arduino at 3.3V +-------------------------- + +Information on it can be found in this doc: :doc:`/supported_hw/supported_prog/serprog/arduino_flasher_3.3v` + +5V arduino with level shifter +----------------------------- + +For detailed instructions on how to use different Arduino models to access SPI flash chips see :doc:`/supported_hw/supported_prog/serprog/arduino_flasher` + +.. image:: 300px-Serprog_0001.jpeg + +Teensy 3.1 SPI + LPC/FWH Flasher +-------------------------------- + +A Teensy 3.1 based small flasher by Urja Rannikko documented here: :doc:`/supported_hw/supported_prog/serprog/teensy_3_1` + +HydraBus multi-tool +------------------- + +HydraBus (hardware) with HydraFW (firmware) is an open source multi-tool for learning, developing, debugging, hacking and penetration testing +of embedded hardware. It is built upon an ARM Cortex-M4 (STM32F405). The source code for HydraFW is available +`on GitHub <https://github.com/hydrabus/hydrafw>`_. Refer to `their GitHub Wiki <https://github.com/hydrabus/hydrafw/wiki/HydraFW-SPI-guide#flashrom-usage>`_ +for more details on how to use HydraBus with flashrom. + +.. image:: 300px-HydraFW_Default_PinAssignment.png + +stm32-vserprog by Chi Zhang +----------------------------- + +A powerful option is `stm32-vserprog <https://github.com/dword1511/stm32-vserprog#stm32-vserprog>`_, a firmware for various STM32-based boards +that turns them into serprog-based programmers with SPI clock speeds up to 36 MHz. diff --git a/doc/supported_hw/supported_prog/serprog/serprog-protocol.rst b/doc/supported_hw/supported_prog/serprog/serprog-protocol.rst new file mode 100644 index 0000000..35574fa --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/serprog-protocol.rst @@ -0,0 +1,150 @@ +===================================== +Serial Flasher Protocol Specification +===================================== + +Version 1 (0x01 return value == 1) +================================== + +Command And Answer Sequence - all commands give an answer. + +PC: COMMAND(8bit) <parameters determined by opcode> + +DEV: ACK/NAK(8bit) <OPTIONAL RETURN BYTES (only if ACK)> / nothing + +Command 0x10 (SYNCNOP) has a special return of NAK+ACK for synchronization. + +ACK = 0x06 + +NAK = 0x15 + +All multibyte values are little-endian. Addresses and lengths are 24-bit. + +======== =============================== ================================================== ================================================= +COMMAND Description Parameters Return Value +======== =============================== ================================================== ================================================= +0x00 NOP none ACK +0x01 Query programmer iface version none ACK + 16bit version (nonzero) +0x02 Query supported commands bitmap none ACK + 32 bytes (256 bits) of supported cmds flags +0x03 Query programmer name none ACK + 16 bytes string (null padding) / NAK +0x04 Query serial buffer size none ACK + 16bit size / NAK +0x05 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK +0x06 Query connected address lines none ACK + 8bit line count / NAK +0x07 Query operation buffer size none ACK + 16bit size / NAK +0x08 Query maximum write-n length none ACK + 24bit length (0==2^24) / NAK +0x09 Read byte 24-bit addr ACK + BYTE / NAK +0x0A Read n bytes 24-bit addr + 24-bit length ACK + length bytes / NAK +0x0B Initialize operation buffer none ACK / NAK +0x0C Write to opbuf: Write byte 24-bit addr + 8-bit byte ACK / NAK (NOTE: takes 5 bytes in opbuf) +0x0D Write to opbuf: Write n 24-bit length + 24-bit addr + length bytes of data ACK / NAK (NOTE: takes 7+n bytes in opbuf) +0x0E Write to opbuf: delay 32-bit usecs ACK / NAK (NOTE: takes 5 bytes in opbuf) +0x0F Execute operation buffer none ACK / NAK +0x10 Sync NOP none NAK + ACK (for synchronization) +0x11 Query maximum read-n length none ACK + 24-bit length (0==2^24) / NAK +0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK +0x13 Perform SPI operation 24-bit slen + 24-bit rlen + slen bytes of data ACK + rlen bytes of data / NAK +0x14 Set SPI clock frequency in Hz 32-bit requested frequency ACK + 32-bit set frequency / NAK +0x15 Toggle flash chip pin drivers 8-bit (0 disable, else enable) ACK / NAK +0x16 Set SPI Chip Select 8-bit ACK / NAK +0x17 Set SPI Mode 8-bit ACK / NAK +0x18 Set CS Mode 8-bit ACK / NAK +0x?? unimplemented command - invalid +======== =============================== ================================================== ================================================= + +Additional information of the above commands: + + About unimplemented commands / startup sequence: + Only commands allowed to be used without checking anything are 0x00,0x10 and 0x01 (NOP,SYNCNOP,Q_IFACE). + If 0x01 doesn't return 1, dont do anything if you dont support a newer protocol. + Then, check support for any other opcode (except 0x02) by using 0x02 (Q_CMDMAP). + + 0x02 (Q_CMDMAP): + The map's bits are mapped as follows: + cmd 0 support: byte 0 bit 0 + cmd 1 support: byte 0 bit 1 + cmd 7 support: byte 0 bit 7 + cmd 8 support: byte 1 bit 0, and so on. + + 0x04 (Q_SERBUF): + If the programmer has a guaranteed working flow control, + it should return a big bogus value - eg 0xFFFF. + + 0x05 (Q_BUSTYPE): + The bit's are defined as follows: + bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI. + + 0x06 (Q_CHIPSIZE): + Only applicable to parallel programmers. + An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap. + + 0x08 (Q_WRNMAXLEN): + If a programmer reports a bigger maximum write-n length than the serial buffer size, + it is assumed that the programmer can process the data fast enough to take in the + reported maximum write-n without problems. + + 0x0F (O_EXEC): + Execute operation buffer will also clear it, regardless of the return value. + + 0x11 (Q_RDNMAXLEN): + If this command is not supported, assume return of 0 (2^24). + + 0x12 (S_BUSTYPE): + Set's the used bustype if the programmer can support more than one flash protocol. + Sending a byte with more than 1 bit set will make the programmer decide among them + on it's own. Bit values as with Q_BUSTYPE. + + 0x13 (O_SPIOP): + Send and receive bytes via SPI. + Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used + to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. + This operation is immediate, meaning it doesn't use the operation buffer. + + 0x14 (S_SPI_FREQ): + Set the SPI clock frequency. The 32-bit value indicates the + requested frequency in Hertz. Value 0 is reserved and should + be NAKed by the programmer. The requested frequency should be + mapped by the programmer software to a supported frequency + lower than the one requested. If there is no lower frequency + available the lowest possible should be used. The value + chosen is sent back in the reply with an ACK. + + 0x15 (S_PIN_STATE): + Sets the state of the pin drivers connected to the flash chip. Disabling them allows other + devices (e.g. a mainboard's chipset) to access the chip. This way the serprog controller can + remain attached to the flash chip even when the board is running. The user is responsible to + NOT connect VCC and other permanently externally driven signals to the programmer as needed. + If the value is 0, then the drivers should be disabled, otherwise they should be enabled. + + 0x16 (S_SPI_CS): + Set which SPI Chip Select pin to use. This operation is immediate, + meaning it doesn't use the operation buffer. + + 0x17 (S_SPI_MODE): + Set which SPI Mode to use for 0x13 O_SPIOP commands. + This operation is immediate, meaning it doesn't use the operation buffer. + The current defined modes are: + + * 0x00: SPI Half Duplex (default) + * 0x01: SPI Full Duplex + + 0x18 (S_CS_MODE): + Set which CS Mode to use. The CS Mode determines the CS behaviour. + This allows manual control over the CS. + This operation is immediate, meaning it doesn't use the operation buffer. + The current defined modes are: + + * 0x00: CS Auto Mode. The CS gets selected before 0x13 O_SPIOP commands and + deselected afterwards. (default) + * 0x01: CS Selected. The CS will be selected until another mode is set. + * 0x02: CS Deselected. The CS will be deselected until another mode is set. + + About mandatory commands: + The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, + but one can't really do anything with these commands. + Support for the following commands is necessary for flashrom to operate properly: + S_CMD_Q_SERBUF, S_CMD_Q_OPBUF, S_CMD_Q_WRNMAXLEN, S_CMD_R_BYTE, + S_CMD_R_NBYTES, S_CMD_O_INIT, S_CMD_O_WRITEB, S_CMD_O_WRITEN, + S_CMD_O_DELAY, S_CMD_O_EXEC. + In addition, support for these commands is recommended: + S_CMD_Q_PGMNAME, S_CMD_Q_BUSTYPE, S_CMD_Q_CHIPSIZE (if parallel). + +See also ``serprog.c`` diff --git a/doc/supported_hw/supported_prog/serprog/teensy_3_1.rst b/doc/supported_hw/supported_prog/serprog/teensy_3_1.rst new file mode 100644 index 0000000..2336387 --- /dev/null +++ b/doc/supported_hw/supported_prog/serprog/teensy_3_1.rst @@ -0,0 +1,81 @@ +================================ +Teensy 3.1 SPI + LPC/FWH Flasher +================================ + +Note: this was made for the Teensy 3.1, but 3.2 should be compatible too. + +Hardware +======== + +.. image:: 300px-Teensy31_lpcspi_flasher.jpg + +The hardware is made of a `Teensy 3.1 <https://www.pjrc.com/teensy/teensy31.html>`_ and a shield-like PCB over it. +Schematic and board files for the PCB can be found `in the github <https://github.com/urjaman/frser-teensyflash/tree/master/hardware>`_. +The PCB is also shared `at OshPark <https://oshpark.com/shared_projects/izukIxq8>`_. + +Other components required: + +* pin headers (total 28, but get more) +* a DIL8 socket (if you want to use SPI DIL8) +* a PLCC32 SMD socket (if you want to use LPC/FWH) +* optional: small SMD capacitor - pad exists under the shield PCB + +Assembly +-------- + +* start by installing the SMD cap (if available) and the DIL8 socket on the shield PCB +* split appropriate strips of pin headers for the teensy and solder them on the teensy, you can use the shield pcb to align them + + * my arrangement was as pictured in order to have more ground clearance under the teensy for the prog button + +* push the shield pcb only a little bit on the pin headers, just so the headers dont come over the top of the PCB +* solder two corner pins to keep the shield PCB in place, these can be done from above +* solder the rest of headers from the underside while watching that you dont flood the topside with too much solder, especially for the ones close to the PLCC socket +* in order to solder the SMD PLCC32 socket, you'll need to break out the middle plastic bit, but keep it safe + + * to protect from solder bridges forming between the pin headers and PLCC socket, i placed a very thin tape over the pin header holes on the pcb during the soldering + * notice that the PLCC footprint isnt centered on the PCB, meaning dont try to align the PLCC socket exactly on the PCB + +* after soldering the PLCC socket, i installed the plastic bit back with a little bit of glue + +Software +======== + +Firmware for the Teensy is available at https://github.com/urjaman/frser-teensyflash + +Also see the README in that directory, both it or this document might be outdated ;) + +As of writing the setup would be: + +* download arduino, extract it somewhere where you have write access +* download the `Teensyduino thingy <https://www.pjrc.com/teensy/td_download.html>`_ +* run it on that arduino tree +* install the udev rules provided in the above url +* compile and install the `teensy_loader_cli <https://www.pjrc.com/teensy/loader_cli.html>`_ in your path + + :: + + git clone --recursive https://github.com/urjaman/frser-teensyflash.git + cd frser-teensyflash + nano Makefile # Edit the TEENSYDIR path to include your arduino directory + make + make program-cli # If this waits you need to press the PROG button on the teensy + +After this you should be able to use it with flashrom serprog, for speedups and enhancements to serprog before they're upstreamed +I'd suggest to use this flashrom tree: https://github.com/urjaman/flashrom/tree/sp-upstream3 + +Device should be something like /dev/ttyACM0 and the baudrate doesnt matter:: + + flashrom -p serprog:dev=/dev/ttyACM0:2000000 + +ISP Usage +--------- + +The same software could be used on a bare teensy 3.1 for ISP SPI programming - this is untested and also the 3.3V supply in the teensy is not strong, so beware, but the SPI pins used would be: + +* CS: "Pin 2", PD0 +* SCK: "Pin 14", PD1 +* MOSI: "Pin 7", PD2 +* MISO: "Pin 8", PD3 + +See https://forum.pjrc.com/threads/25643-Combined-Pin-Assignments-card for a good Teensy pinmap picture. -- To view, visit https://review.coreboot.org/c/flashrom/+/82018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie52f1e051ed215d61d5fb535e3eddeac71f64d13 Gerrit-Change-Number: 82018 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Sydney <git(a)funkeleinhorn.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: J. Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: merged

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[S] Change in flashrom[main]: flashchips.c: Add support for XM25RU256C
by Georg Gottleuber (Code Review) 06 May '24

06 May '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Georg Gottleuber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82101?usp=email ) Change subject: flashchips.c: Add support for XM25RU256C ...................................................................... Patch Set 2: (3 comments) Patchset: PS1: > Thank you! Do you have a link to the datasheet for the chip? I have personally asked for the datasheet, but I don't know if it is okay to publish it. XM25RU256C is very similar to XM25QU256C. Patchset: PS2: Thank you for the quick review. File flashchips.c: https://review.coreboot.org/c/flashrom/+/82101/comment/82916e6e_ac7f0dcf : PS1, Line 21731: TEST_UNTESTED > You tested it, from the logs your provided you did probe, read, write, so this should be `TEST_OK_PR […] OK, I was unsure how this review process works and didn't want to force two steps at once. See patchset v2... -- To view, visit https://review.coreboot.org/c/flashrom/+/82101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I431474a662304d09438e274706d3fc9cfbbe0bd6 Gerrit-Change-Number: 82101 Gerrit-PatchSet: 2 Gerrit-Owner: Georg Gottleuber <ggo(a)tuxedo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 06 May 2024 08:25:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging.
by ZhiYuanNJ (Code Review) 06 May '24

06 May '24

Attention is currently required from: Nicholas Chin. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82193?usp=email to look at the new patch set (#5). Change subject: ch347_spi: Add driver support for CH347F packaging. ...................................................................... ch347_spi: Add driver support for CH347F packaging. Bug fix: fix SPI clock settings errors. CH347F can work simultaneously with SPI, I2C and other signals. CH347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Signed-off-by: ZhiYuanNJ <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 66 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82193/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 5 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: ch347_spi: Fix CH347T PID, interface, and clock settings errors
by ZhiYuanNJ (Code Review) 06 May '24

06 May '24

Attention is currently required from: Nicholas Chin. ZhiYuanNJ has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Fix CH347T PID, interface, and clock settings errors ...................................................................... Patch Set 4: (13 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/82193/comment/67c31ce5_f0f8db70 : PS2, Line 7: Bug fix: Fix CH347T PID, interface, and clock settings errors > The typical commit message style is `<component>: Short description (up to 72 characters)` (see http […] Done https://review.coreboot.org/c/flashrom/+/82193/comment/f52a18e7_811f32e0 : PS2, Line 10: The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C > Please reflow to 72 characters per line Done https://review.coreboot.org/c/flashrom/+/82193/comment/3f0781e7_f90e257e : PS2, Line 10: The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C > Please reflow to 72 characters per line Done https://review.coreboot.org/c/flashrom/+/82193/comment/839a99e2_9f45ebf0 : PS2, Line 12: ?from=search&wd=eyJpdiI6Im4zdVRJdHdpNks1WUFLSUFDNnRsYnc9PSIsInZhbHVlIjoicHFsU3EwQlgzWmgzM1ZIYnBpZXFiUT09IiwibWFjIjoiNjZjNjc5ZDQ4Yzg2ZDdhNzc5YzM4OTA0MTlkM2FiYWQ1Yzg0ZTZkNWNiZDczZDM1NjM1ODIwN2NjZDhlOTNmOCJ9 > Everything from the `?` onwards isn't necessary to navigate to the product page Done https://review.coreboot.org/c/flashrom/+/82193/comment/d28deb28_ee982ff6 : PS2, Line 12: ?from=search&wd=eyJpdiI6Im4zdVRJdHdpNks1WUFLSUFDNnRsYnc9PSIsInZhbHVlIjoicHFsU3EwQlgzWmgzM1ZIYnBpZXFiUT09IiwibWFjIjoiNjZjNjc5ZDQ4Yzg2ZDdhNzc5YzM4OTA0MTlkM2FiYWQ1Yzg0ZTZkNWNiZDczZDM1NjM1ODIwN2NjZDhlOTNmOCJ9 > Everything from the `?` onwards isn't necessary to navigate to the product page Done File ch347_spi.c: PS2: > I would split the spispeed changes into a separate patch so that this one is just about adding the C […] Do I need to open a separate submission for the issue of device speed settings in this submission? PS2: > Please use the `/* comment */` comment style rather than `//coment` for consistency with the rest of […] Done https://review.coreboot.org/c/flashrom/+/82193/comment/0f24d584_716d43e1 : PS2, Line 10: * : * CH347 is a high-speed USB bus converter chip that provides UART, I2C : * and SPI synchronous serial ports and JTAG interface through USB bus. : * : * The SPI interface by CH347 can supports transmission frequency : * configuration up to 60MHz. : * : * The USB2.0 to spi scheme based on CH347 can be used to build : * customized USB high-speed spi debugger and other products. : * : * _____________ : * | |____SPI (MISO,MOSI,SCK,CSC0,CSC1) : * USB__| CH347T/F | : * |_____________|____(UART/I2C/JTAG/SWD/GPIO) : * ______|______ : * | | : * | 8 MHz XTAL | : * |_____________| : * > This should be placed after the licence header, not in the middle of it. […] Done https://review.coreboot.org/c/flashrom/+/82193/comment/bf99344c_d7c39384 : PS2, Line 79: 0x55DD > This should be left at 0x55DB, which corresponds to mode 1. […] Thank you for the reminder, Corrected. https://review.coreboot.org/c/flashrom/+/82193/comment/f8ba5ba6_63cbd15e : PS2, Line 97: 2, //CH347T interface number : 4, //CH347F interface number > Use the `CH347*_IFACE` defines from above? That also removes the need for the comments Done https://review.coreboot.org/c/flashrom/+/82193/comment/746e374c_59713052 : PS2, Line 344: Couldn't open device %04x:%04x.\n > This block of code would only run if flashrom has gone through all the IDs in `devs_ch347_spi` and w […] Done https://review.coreboot.org/c/flashrom/+/82193/comment/e1d9326d_fb4eea64 : PS2, Line 347: > Remove trailing whiespace Done https://review.coreboot.org/c/flashrom/+/82193/comment/00c2db12_1d74593c : PS2, Line 356: Failed to claim interface 2 > Update this to reflect the actual interface number being used Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 4 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 06 May 2024 06:23:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: ch347_spi: Fix CH347T PID, interface, and clock settings errors
by ZhiYuanNJ (Code Review) 06 May '24

06 May '24

Attention is currently required from: ZhiYuanNJ. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82193?usp=email to look at the new patch set (#4). Change subject: ch347_spi: Fix CH347T PID, interface, and clock settings errors ...................................................................... ch347_spi: Fix CH347T PID, interface, and clock settings errors Add functionality : Add driver support for CH347F packaging. CH347F can work simultaneously with SPI, I2C and other signals. CH347 introduce is available at the following URL: https://www.wch-ic.com/products/CH347.html Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Signed-off-by: ZhiYuanNJ <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 66 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82193/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 4 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-MessageType: newpatchset

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[M] Change in flashrom[main]: Bug fix: Fix CH347T PID, interface, and clock settings errors
by Nicholas Chin (Code Review) 06 May '24

06 May '24

Attention is currently required from: ZhiYuanNJ. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: Bug fix: Fix CH347T PID, interface, and clock settings errors ...................................................................... Patch Set 2: (12 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/82193/comment/2e932e8c_c09e281c : PS2, Line 7: Bug fix: Fix CH347T PID, interface, and clock settings errors The typical commit message style is `<component>: Short description (up to 72 characters)` (see https://www.flashrom.org/dev_guide/development_guide.html#commit-message-1) In this case, the component would be `ch347_spi`, and the description could be something like `Add support for QFN28 package (CH347F)`. Then the next line about `Add functionality` can be dropped. As I note later, I would move the spispeed changes to a separate patch. https://review.coreboot.org/c/flashrom/+/82193/comment/5bfef957_13d3e12e : PS2, Line 10: The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C Please reflow to 72 characters per line https://review.coreboot.org/c/flashrom/+/82193/comment/db3dcde1_71e49d49 : PS2, Line 12: ?from=search&wd=eyJpdiI6Im4zdVRJdHdpNks1WUFLSUFDNnRsYnc9PSIsInZhbHVlIjoicHFsU3EwQlgzWmgzM1ZIYnBpZXFiUT09IiwibWFjIjoiNjZjNjc5ZDQ4Yzg2ZDdhNzc5YzM4OTA0MTlkM2FiYWQ1Yzg0ZTZkNWNiZDczZDM1NjM1ODIwN2NjZDhlOTNmOCJ9 Everything from the `?` onwards isn't necessary to navigate to the product page Patchset: PS2: Hello! Thanks for the patch! File ch347_spi.c: PS2: I would split the spispeed changes into a separate patch so that this one is just about adding the CH347F variant. PS2: Please use the `/* comment */` comment style rather than `//coment` for consistency with the rest of the file https://review.coreboot.org/c/flashrom/+/82193/comment/a30520cf_e5b36fc0 : PS2, Line 10: * : * CH347 is a high-speed USB bus converter chip that provides UART, I2C : * and SPI synchronous serial ports and JTAG interface through USB bus. : * : * The SPI interface by CH347 can supports transmission frequency : * configuration up to 60MHz. : * : * The USB2.0 to spi scheme based on CH347 can be used to build : * customized USB high-speed spi debugger and other products. : * : * _____________ : * | |____SPI (MISO,MOSI,SCK,CSC0,CSC1) : * USB__| CH347T/F | : * |_____________|____(UART/I2C/JTAG/SWD/GPIO) : * ______|______ : * | | : * | 8 MHz XTAL | : * |_____________| : * This should be placed after the licence header, not in the middle of it. Also, I'm not sure this text really adds any value in the first place. https://review.coreboot.org/c/flashrom/+/82193/comment/6f0d657b_5ad5d4c6 : PS2, Line 79: 0x55DD This should be left at 0x55DB, which corresponds to mode 1. 0x55DD corresponds to mode 3, which does not support SPI https://review.coreboot.org/c/flashrom/+/82193/comment/f2521d3c_87af01f6 : PS2, Line 97: 2, //CH347T interface number : 4, //CH347F interface number Use the `CH347*_IFACE` defines from above? That also removes the need for the comments https://review.coreboot.org/c/flashrom/+/82193/comment/ae96164a_82bf0b50 : PS2, Line 344: Couldn't open device %04x:%04x.\n This block of code would only run if flashrom has gone through all the IDs in `devs_ch347_spi` and wasn't able to open any of them. So a generic message saying it couldn't find a CH347 would probably be more appropriate compared to saying it couldn't open a particular ID (which in this case would be whatever is the last vid and pid in the list) https://review.coreboot.org/c/flashrom/+/82193/comment/807eb57f_4a629f18 : PS2, Line 347: Remove trailing whiespace https://review.coreboot.org/c/flashrom/+/82193/comment/22f87e53_3a0f7ace : PS2, Line 356: Failed to claim interface 2 Update this to reflect the actual interface number being used -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 2 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Mon, 06 May 2024 04:42:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: flashrom: Don't throw around "delay 1 second" so lightly
by Peter Marheine (Code Review) 06 May '24

06 May '24

Attention is currently required from: Anastasia Klimchuk, Brian Norris. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: flashrom: Don't throw around "delay 1 second" so lightly ...................................................................... Patch Set 5: (1 comment) Patchset: PS1: > > I think that recommendation should be captured in some kind of changelog so there's "real" documen […] Angel's suggestion (on the list) to continue using the delay for `!BUS_NONSPI` seems like a reasonable compromise between safety and wastefulness (and should work for all the programmers that ChromeOS cares about). Do you plan to make that change? -- To view, visit https://review.coreboot.org/c/flashrom/+/80807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Gerrit-Change-Number: 80807 Gerrit-PatchSet: 5 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 May 2024 03:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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