Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55115 )
Change subject: programmer_table: remove NULL termination
......................................................................
programmer_table: remove NULL termination
The {0} Object at the end of programmer_table which correspond
to PROGRAMMER_INVALID has no use in currend code
Change-Id: Ib63c2d2941f23a0788e26e5a5feb25d8669acb42
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.de>
---
M flashrom.c
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/55115/1
diff --git a/flashrom.c b/flashrom.c
index 0af5057..65f7e73 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -532,8 +532,6 @@
.delay = internal_delay,
},
#endif
-
- {0}, /* This entry corresponds to PROGRAMMER_INVALID. */
};
#define SHUTDOWN_MAXFN 32
@@ -2191,7 +2189,7 @@
/* Safety check. Instead of aborting after the first error, check
* if more errors exist.
*/
- if (ARRAY_SIZE(programmer_table) - 1 != PROGRAMMER_INVALID) {
+ if (ARRAY_SIZE(programmer_table) != PROGRAMMER_INVALID) {
msg_gerr("Programmer table miscompilation!\n");
ret = 1;
}
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ib63c2d2941f23a0788e26e5a5feb25d8669acb42
Gerrit-Change-Number: 55115
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas Heijligen <src(a)posteo.de>
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Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55107 )
Change subject: nic3com.c: Allocate data and register shutdown at the end of init
......................................................................
Patch Set 1: -Code-Review
(1 comment)
File nic3com.c:
https://review.coreboot.org/c/flashrom/+/55107/comment/b6379f3c_f06483f6
PS1, Line 151: data->id = id;
just put the above line below this line and squash into the previous patch.
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I9834b82650cd070556cf82207796bc6bd6b31b28
Gerrit-Change-Number: 55107
Gerrit-PatchSet: 1
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55108 )
Change subject: nicrealtek.c: Refactor singleton states into reentrant pattern
......................................................................
nicrealtek.c: Refactor singleton states into reentrant pattern
Move global singleton states into a struct and store within
the par_master data field for the life-time of the driver.
This is one of the steps on the way to move par_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".
BUG=b:185191942
TEST=builds
Change-Id: If0cb0fefb53b2c6bb65a85f4c8dc6f323954dd0c
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M nicrealtek.c
1 file changed, 31 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/55108/1
diff --git a/nicrealtek.c b/nicrealtek.c
index 788c088..544abab 100644
--- a/nicrealtek.c
+++ b/nicrealtek.c
@@ -24,8 +24,11 @@
#define PCI_VENDOR_ID_REALTEK 0x10ec
#define PCI_VENDOR_ID_SMC1211 0x1113
-static uint32_t io_base_addr = 0;
-static int bios_rom_addr, bios_rom_data;
+struct nicrealtek_data {
+ uint32_t io_base_addr;
+ int bios_rom_addr;
+ int bios_rom_data;
+};
const struct dev_entry nics_realtek[] = {
{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
@@ -37,38 +40,41 @@
static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
{
+ struct nicrealtek_data *data = flash->mst->par.data;
+
/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
- io_base_addr + bios_rom_addr);
+ data->io_base_addr + data->bios_rom_addr);
/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + bios_rom_addr);
+ data->io_base_addr + data->bios_rom_addr);
}
static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
{
+ struct nicrealtek_data *data = flash->mst->par.data;
uint8_t val;
/* FIXME: Can we skip reading the old data and simply use 0? */
/* Read old data. */
- val = INB(io_base_addr + bios_rom_data);
+ val = INB(data->io_base_addr + data->bios_rom_data);
/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
- io_base_addr + bios_rom_addr);
+ data->io_base_addr + data->bios_rom_addr);
/* Read new data. */
- val = INB(io_base_addr + bios_rom_data);
+ val = INB(data->io_base_addr + data->bios_rom_data);
/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
* enable software access.
*/
OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + bios_rom_addr);
+ data->io_base_addr + data->bios_rom_addr);
return val;
}
@@ -87,12 +93,16 @@
static int nicrealtek_shutdown(void *data)
{
/* FIXME: We forgot to disable software access again. */
+ free(data);
return 0;
}
int nicrealtek_init(void)
{
struct pci_dev *dev = NULL;
+ uint32_t io_base_addr = 0;
+ int bios_rom_addr;
+ int bios_rom_data;
if (rget_io_perms())
return 1;
@@ -119,10 +129,21 @@
break;
}
- if (register_shutdown(nicrealtek_shutdown, NULL))
+ struct nicrealtek_data *data = calloc(1, sizeof(*data));
+ if (!data) {
+ msg_perr("Unable to allocate space for PAR master data\n");
return 1;
+ }
+ data->io_base_addr = io_base_addr;
+ data->bios_rom_addr = bios_rom_addr;
+ data->bios_rom_data = bios_rom_data;
- register_par_master(&par_master_nicrealtek, BUS_PARALLEL, NULL);
+ if (register_shutdown(nicrealtek_shutdown, data)) {
+ free(data);
+ return 1;
+ }
+
+ register_par_master(&par_master_nicrealtek, BUS_PARALLEL, data);
return 0;
}
--
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