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Change subject: ch347_spi: Add driver support for CH347F packaging
......................................................................
Patch Set 7:
(1 comment)
File ch347_spi.c:
PS2:
> Done
Yes, please move the code for the device speed settings to a new commit and push another patch to Gerrit.
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Change subject: flashrom_udev.rules: Add rule for CH347
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Nicholas, just wanted to check, is this patch ready, can I submit?
Yes, this patch can be submitted.
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Change subject: flashchips: Add (or update) chip models <list models>
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/82332/comment/a4cc4023_cc188528 :
PS1, Line 7: Add (or update) chip models <list models>
For this commit you can be more specific, because you know what model you adding. So instead the title (title is first line) should be:
`flashchips: Add support for GD25LF128E`
The rest of commit message is all good, keep it.
Patchset:
PS1:
Great, you are getting closer, this patch is almost there! I added two comments what you need to do.
If you have questions, you can reply to comments (Reply button on the comment and then Reply blue button on the top).
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/82332/comment/5af4ddef_435fc060 :
PS1, Line 6506: .model_id = GIGADEVICE_GD25LF128E,
This macro should be added in the same patch as chip definition.
So you need to add to this commit a change in include/flashchips.h , one line adding this macro for this model ID.
I can see you made CB:82190 with all the model IDs added, but you will need to add IDs in the same patch where the chip definition is added.
As an example, if you remember the other patch that was discussed on the mailing list: CB:58025. It's an example, but you can see it adds two chip definitions in flashchips.c, and two model IDs in flashchips.h.
In this patch, you will have one definition and one new model ID for it.
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Change subject: flashchips: use 4BA direct erase functions for MX25L256
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Is anyone still interested in this patch? (and it's on staging branch)
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Change subject: flashrom-tester: Include flashrom/src/cmd.rs tests in Cargo workspace
......................................................................
flashrom-tester: Include flashrom/src/cmd.rs tests in Cargo workspace
Ensure ChromeOS ebuild (ecargo_test) runs all unit tests, including
those under flashrom/src/cmd.rs which were previously being skipped due
to not being in the default Cargo workspace.
By adding flashrom/ to the [workspace] section of Cargo.toml, these
tests will now be consistently included when building and testing
flashrom-tester on ChromeOS.
References:
* ebuild of flashrom-tester: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/…
* ecarg_test: https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/…
BUG=b:338962302
TEST=(ChromeOS)
FEATURES=`test emerge-corsola flashrom-tester`
Could see tests like `cmd::tests::decode_io_opt ... ok`
TEST=(UPSTREAM)
1. Build flashrom by `meson`
2. Build bindings/rust/libflashrom by `cargo build`
3. Build util/flashrom_tester by
`cargo build`
`cargo test --workspace`
Could see tests like `cmd::tests::decode_io_opt ... ok`
Change-Id: Ic23bc35592e6d7d8dd24c71630ea9a2eb2d58573
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82231
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/flashrom_tester/Cargo.toml
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
Angel Pons: Looks good to me, but someone else must approve
Anastasia Klimchuk: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/util/flashrom_tester/Cargo.toml b/util/flashrom_tester/Cargo.toml
index a76a5b4..50c73dd 100644
--- a/util/flashrom_tester/Cargo.toml
+++ b/util/flashrom_tester/Cargo.toml
@@ -15,6 +15,9 @@
name = "flashrom_tester"
required-features = ["cli"]
+[workspace]
+members = [".", "flashrom"]
+
[dependencies]
atty = "0.2"
built = { version = "0.5", features = ["chrono"] }
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Change subject: erasure_layout: don't copy region buffers if they're null/zero-size
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/81548/comment/fd0cc90d_526bab2a :
PS2, Line 10: the pointer is null
I think from the meaning of the patch, you meant to say
`the pointer is non-null`
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/81548/comment/7680b945_70a9f658 :
PS1, Line 263: old_start_buf = (uint8_t *)malloc(old_start - region_start);
: if (!old_start_buf) {
: msg_cerr("Not enough memory!\n");
: ret = -1;
: goto _end;
: }
: old_end_buf = (uint8_t *)malloc(region_end - old_end);
: if (!old_end_buf) {
: msg_cerr("Not enough memory!\n");
: ret = -1;
: goto _end;
: }
> Sorry it took longer than I expected. […]
Great! this is what I was thinking about! I am resolving this comment.
I added few more other comments though :)
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/81548/comment/dd093a22_69ec2718 :
PS2, Line 263: size_t old_start_len
This can be const, but also
maybe rename it into `start_buf_len` ?
I think that "old" suffix doesn't really explain anything. What do you think?
https://review.coreboot.org/c/flashrom/+/81548/comment/47062ded_d9a3f306 :
PS2, Line 264: size_t old_end_len
And this can be const and `end_buf_len`
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Change subject: flashrom_udev.rules: Add rule for CH347
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Nicholas, just wanted to check, is this patch ready, can I submit?
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Change subject: flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME
......................................................................
Patch Set 8:
(10 comments)
Patchset:
PS8:
> I read through the comments thread to recall what the patch have been waiting for. […]
Many thanks to Victor on the mailing list for giving datasheets, I did a review and added some comments.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58025/comment/76651360_3fec0d74 :
PS8, Line 6552: .name = "GD25LR256E",
This is out of order, both entries need to be moved after GD25LQ80 and just before GD25Q10
https://review.coreboot.org/c/flashrom/+/58025/comment/0deca606_33434b56 :
PS8, Line 6590: SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD
Datasheet has BP4, so this should be `SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD`
https://review.coreboot.org/c/flashrom/+/58025/comment/343681e1_32b6595a :
PS8, Line 6591: SPI_DISABLE_BLOCKPROTECT
SPI_DISABLE_BLOCKPROTECT_BP4_SRWD
https://review.coreboot.org/c/flashrom/+/58025/comment/e256659a_175ff710 :
PS8, Line 6594: {1600, 2000}
Slight correction : from datasheet it's 1.65~2.0V
https://review.coreboot.org/c/flashrom/+/58025/comment/69474edd_5fc8758d :
PS8, Line 6599: .tb = {STATUS1, 6, RW},
In such cases you should add a comment:
`Called BP4 in datasheet, acts like TB`
https://review.coreboot.org/c/flashrom/+/58025/comment/4ea82095_fcd0841a :
PS8, Line 6646: SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD
SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD
https://review.coreboot.org/c/flashrom/+/58025/comment/f67121aa_1a0a7e2d :
PS8, Line 6647: SPI_DISABLE_BLOCKPROTECT
SPI_DISABLE_BLOCKPROTECT_BP4_SRWD
https://review.coreboot.org/c/flashrom/+/58025/comment/b194c85c_4bf5c3fd :
PS8, Line 6650: {1600, 2000},
1.65~2.0V
https://review.coreboot.org/c/flashrom/+/58025/comment/410965dc_2c5da58a :
PS8, Line 6655: .tb = {STATUS1, 6, RW},
Also as above, needs a comment:
`Called BP4 in datasheet, acts like TB`
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