Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55694 )
Change subject: Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
......................................................................
Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
This reverts commit ba6575de82f091b97ea0f2efcf2f79ef3739d64f.
Technically, the only thing that is wrong here is the lack of docu-
mentation (manpage update). However, as this change was succeeded by
a regressing fixup patch, it seems likely that the meaning of the
`csgpiol` parameter was just misunderstood and these changes were
not what the author intended.
Change-Id: I460237b9d275b1cd1d8a069f852d17dea393b14e
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55694
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M ft2232_spi.c
1 file changed, 14 insertions(+), 26 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 44975db..eb98933 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -88,17 +88,10 @@
/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
* sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * TCK/SK is bit 0.
- * TDI/DO is bit 1.
- * TDO/DI is bit 2.
- * TMS/CS is bit 3.
- * GPIOL0 is bit 4.
- * GPIOL1 is bit 5.
- * GPIOL2 is bit 6.
- * GPIOL3 is bit 7.
- *
- * The pin signal direction bit offsets follow the same order; 0 means that
- * pin at the matching bit index is an input, 1 means pin is an output.
+ * SCK is bit 0.
+ * DO is bit 1.
+ * DI is bit 2.
+ * CS is bit 3.
*
* The default values (set below in ft2232_spi_init) are used for most devices:
* value: 0x08 CS=high, DI=low, DO=low, SK=low
@@ -459,24 +452,19 @@
}
free(arg);
- /* Allows setting multiple GPIOL states, for example: csgpiol=012 */
arg = extract_programmer_param("csgpiol");
if (arg) {
- unsigned int ngpios = strlen(arg);
- for (unsigned int i = 0; i <= ngpios; i++) {
- int temp = arg[i] - '0';
- if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) {
- msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n"
- "Valid values are numbers between 0 and 3. "
- "Multiple GPIOLs can be specified.\n", arg);
- free(arg);
- return -2;
- } else {
- unsigned int pin = temp + 4;
- cs_bits |= 1 << pin;
- pindir |= 1 << pin;
- }
+ char *endptr;
+ unsigned int temp = strtoul(arg, &endptr, 10);
+ if (*endptr || endptr == arg || temp > 3) {
+ msg_perr("Error: Invalid GPIOL specified: \"%s\".\n"
+ "Valid values are between 0 and 3.\n", arg);
+ free(arg);
+ return -2;
}
+ unsigned int pin = temp + 4;
+ cs_bits |= 1 << pin;
+ pindir |= 1 << pin;
}
free(arg);
--
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Gerrit-Change-Number: 55694
Gerrit-PatchSet: 3
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55683 )
Change subject: ft2232_spi: Don't lower write data chunksize
......................................................................
ft2232_spi: Don't lower write data chunksize
This "chunk size" limits the amount of data that is passed to libusb
at once. If we had exceeded the chunk size, libftdi would have split
the data into individual, synchronous bulk transfers. But the chunk
size was actually chosen to avoid this. So without any known effect,
setting the chunk size is useless. Drop it.
Change-Id: I779e24dc3f3379a98ddce02c3765062ac3241884
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55683
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M ft2232_spi.c
1 file changed, 0 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 3fe7ea4..5b5d3cd 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -651,10 +651,6 @@
msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(&ftdic));
}
- if (ftdi_write_data_set_chunksize(&ftdic, 270)) {
- msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(&ftdic));
- }
-
if (ftdi_set_bitmode(&ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) {
msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(&ftdic));
}
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS4:
> Maybe they are unique. However I have this feeling that DMI checks are more reliable. Do we know whether all vendors set PCI SVID/SDID?
If any vendor does not set the SVID, we could still add DMI in the future if required. For now, this should be safe. Having both DMI and SVID is overkill IMO.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 )
Change subject: ft2232_spi.c: Implement spi_send_multicommand()
......................................................................
Patch Set 36:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/40477/comment/8fee0e1c_f9ec8089
PS35, Line 15: my
> As mentioned elsewhere, specify this is in a virtualized environment?
Elsewhere this was a resolved comment :-P
Done
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Attention is currently required from: Simon Buhrow, Alan Green, Nico Huber, Edward O'Callaghan, Anastasia Klimchuk, Samir Ibradžić.
Nico Huber has uploaded a new patch set (#36) to the change originally created by Simon Buhrow. ( https://review.coreboot.org/c/flashrom/+/40477 )
Change subject: ft2232_spi.c: Implement spi_send_multicommand()
......................................................................
ft2232_spi.c: Implement spi_send_multicommand()
Every ftdi_write_data() call is quite time consuming as the ftdi-chips
seems to take always 2-3ms to respond. This leads to what the comment
already says: Minimize USB transfers by packing as many commands as
possible together. So I packed the WREN command together with the
following operation which can be program or erase operation.
This saves about 1 minute when programming a 128MBit Flash within a
virtualized setup.
Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de>
Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a
---
M ft2232_spi.c
1 file changed, 90 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/40477/36
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