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[L] Change in flashrom[main]: erasure_layout: Fix get_flash_region bug
by Nikolai Artemiev (Code Review) 06 Jun '24

06 Jun '24

Attention is currently required from: Aarya, Alexander Goncharov, Anastasia Klimchuk, Peter Marheine. Nikolai Artemiev has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/82393?usp=email ) Change subject: erasure_layout: Fix get_flash_region bug ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9 Gerrit-Change-Number: 82393 Gerrit-PatchSet: 17 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Wed, 05 Jun 2024 23:55:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Hsuan-ting Chen (Code Review) 05 Jun '24

05 Jun '24

Attention is currently required from: Hsuan Ting Chen. Hello Hsuan Ting Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/82908?usp=email to review the following change. Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... how_to_add_new_chip: Add a section for feature bits and WRSR handling Feature bits are too complicated to understand if we only read the codes/datasheets. Add a new section in how_to_add_new_chip to add more details about each feature bits. Add the detailed explanation for WRSR handling first. If this new section looks good, I'll try to add some more sections in further commits. BUG=b:345154585 TEST=meson compile -C builddir and view the doc. Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> --- M doc/contrib_howtos/how_to_add_new_chip.rst 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/82908/1 diff --git a/doc/contrib_howtos/how_to_add_new_chip.rst b/doc/contrib_howtos/how_to_add_new_chip.rst index b046ac3..ed25d29 100644 --- a/doc/contrib_howtos/how_to_add_new_chip.rst +++ b/doc/contrib_howtos/how_to_add_new_chip.rst @@ -102,6 +102,31 @@ in ``include/flash.h``. Without any tests it should be set to ``TEST_UNTESTED``. See also another doc :doc:`how_to_mark_chip_tested`. +Feature Bits +------------- + +The ``.feature_bits`` field in a chip definition encodes various features using a bitmask. +Here are some of the selected feature bits that need to be highlighted: + +Write-Status-Register (WRSR) Handling +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**. + +The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and +other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits. + +* ``FEATURE_WRSR_EWSR``: + This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the + immediately-followed next WRSR instruction. Usually, the opcode is **0x50**. + +* ``FEATURE_WRSR_WREN``: + This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit + must be set priort to every WRSR command. Usually, the opcode is **0x06**. + +* ``FEATURE_WRSR_EITHER``: + This indicates that either EWSR or WREN is supported in this chip. + Operations ========== -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org>

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[L] Change in flashrom[main]: erasure_layout: Fix get_flash_region bug
by Peter Marheine (Code Review) 05 Jun '24

05 Jun '24

Attention is currently required from: Aarya, Alexander Goncharov, Anastasia Klimchuk, Nikolai Artemiev. Peter Marheine has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/82393?usp=email ) Change subject: erasure_layout: Fix get_flash_region bug ...................................................................... Patch Set 17: (1 comment) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/82393/comment/b65439c5_5ac2466b?us… : PS16, Line 89: printf("Eraser called with blockaddr=0x%x, blocklen=0x%x\n", blockaddr, blocklen); > I only now noticed, perhaps we can log erase_func here too (it is logged in `block_erase_chip_with_p […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9 Gerrit-Change-Number: 82393 Gerrit-PatchSet: 17 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Wed, 05 Jun 2024 06:34:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: erasure_layout: Fix get_flash_region bug
by Peter Marheine (Code Review) 05 Jun '24

05 Jun '24

Attention is currently required from: Aarya, Alexander Goncharov, Anastasia Klimchuk, Nikolai Artemiev, Peter Marheine. Hello Aarya, Alexander Goncharov, Anastasia Klimchuk, Nikolai Artemiev, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82393?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Code-Review+2 by Anastasia Klimchuk, Code-Review+2 by Peter Marheine, Verified+1 by build bot (Jenkins) Change subject: erasure_layout: Fix get_flash_region bug ...................................................................... erasure_layout: Fix get_flash_region bug When flash regions are protected, erase could incorrectly erase regions which were meant to be protected by requesting the correct size but using an erase opcode with coarser granularity than desired (for instance using a 16-byte erase command while attempting to erase only 8 bytes). This fixes that by exchanging the nesting of the loops over erase blocks and flash regions. Old: - Select erasefns - Loop over blocks to erase for each selected erasefn - Loop over programmer flash regions within erase block - Erase regions (may fail since selected erasefn will be too big if flash region is smaller than erase block) New: - Loop over programmer flash regions within erase block - Select erasefns within programer flash region - Loop over blocks to erase for each selected erasefn - Erase regions Eraser selection and erasing has also been factored out into a helper function to manage nesting depth. TEST=New test cases pass, whereas some of them fail without the changes to erasure_layout.c BUG=https://ticket.coreboot.org/issues/525 Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9 Co-authored-by: Nikolai Artemiev <nartemiev(a)google.com> Co-authored-by: Anastasia Klimchuk <aklm(a)flashrom.org> Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M erasure_layout.c M tests/erase_func_algo.c M tests/tests.c M tests/tests.h 4 files changed, 602 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/82393/17 -- To view, visit https://review.coreboot.org/c/flashrom/+/82393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic5bf9d0f0e4a94c48d6f6e74e3cb9cccdc7adec9 Gerrit-Change-Number: 82393 Gerrit-PatchSet: 17 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net>

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[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by ZhiYuanNJ (Code Review) 04 Jun '24

04 Jun '24

Attention is currently required from: Nicholas Chin, ZhiYuanNJ. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82776?usp=email to look at the new patch set (#3). Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... ch347_spi: Add spi clock frequency selection CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use - p ch347_spi:spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 37 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/82776/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 3 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in flashrom[main]: doc: Convert ME and Intel docs
by David Hendricks (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev. David Hendricks has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/82649?usp=email ) Change subject: doc: Convert ME and Intel docs ...................................................................... Patch Set 1: (1 comment) File doc/user_docs/management_engine.rst: PS1: > > Does the coding style guidelines apply to documentation as well? […] Good points. I'd vote for 112 columns to go along with the coding guidelines, though the coding guideline itself seems to go with 120 columns so maybe that's better :-) Anyway, pick *something* that can be auto-enforced to keep the docs uniformly formatted and help any newcomers who might want to contribute to the docs (PRs from Github tended to violate all kinds of style rules, IIRC). -- To view, visit https://review.coreboot.org/c/flashrom/+/82649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I79af5674f3af9ca880e89becd6a272a2cf8ed599 Gerrit-Change-Number: 82649 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 21:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: doc: Convert ME and Intel docs
by Anastasia Klimchuk (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/82649?usp=email ) Change subject: doc: Convert ME and Intel docs ...................................................................... Patch Set 1: (1 comment) File doc/user_docs/management_engine.rst: PS1: > Does the coding style guidelines apply to documentation as well? That's an interesting question! :) I can tell you what the current state is. Major usage for reading docs is on the website. For the website, html is generated from .rst file, and line length doesn't matter. To mark new paragraph, you need to add two line breaks. So in other words, whether line length is 80 or 112 or 200 will produce the same html page. However there is still the way to read docs from the source. GitHub web UI, where we have mirror, by default formats .rst files for preview, so line length again doesn't matter. If you look at raw source, then you have the length of your screen. And lastly, one can read or modify docs from source in the terminal window (I do this often :D ). I usually try make line length so that it's convenient to display in the medium-size laptop screen. So, not too long. But there is no strict reason to limit docs sources to 80 chars, it would leave half screen empty. In any case, thank you so much for review! Also yes, we can improve docs further as a follow-up. -- To view, visit https://review.coreboot.org/c/flashrom/+/82649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I79af5674f3af9ca880e89becd6a272a2cf8ed599 Gerrit-Change-Number: 82649 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:40:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com>

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[M] Change in flashrom[main]: flashchips: Add support for MXIC MX25U25645G
by DZ (Code Review) 03 Jun '24

03 Jun '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82777?usp=email ) Change subject: flashchips: Add support for MXIC MX25U25645G ...................................................................... flashchips: Add support for MXIC MX25U25645G The MX25U25645G has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25U25645G datasheet is available at the following URL: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8… Change-Id: I8641f36e1909274629690fc243be46281a21360d Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c M include/flashchips.h 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/82777/1 diff --git a/flashchips.c b/flashchips.c index a5d9ec2..473e775 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11095,6 +11095,63 @@ { .vendor = "Macronix", + .name = "MX25U25645G", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25U25635F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA | FEATURE_CFGR | FEATURE_SCUR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: security register */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25U3235E/F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index c264b04..0b276e9 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -534,7 +534,7 @@ #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ #define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ #define MACRONIX_MX25U12835E 0x2538 /* Same as MX25U12835F */ -#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G */ +#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G, MX25U25645G */ #define MACRONIX_MX25U51245G 0x253a #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX25L6495F 0x9517 -- To view, visit https://review.coreboot.org/c/flashrom/+/82777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8641f36e1909274629690fc243be46281a21360d Gerrit-Change-Number: 82777 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn>

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[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by ZhiYuanNJ (Code Review) 03 Jun '24

03 Jun '24

ZhiYuanNJ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... ch347_spi: Add spi clock frequency selection CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use - p ch347_spi: spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <871238103(a)qq.com> --- M ch347_spi.c 1 file changed, 35 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/82776/1 diff --git a/ch347_spi.c b/ch347_spi.c index 21dcabb..85435bb 100644 --- a/ch347_spi.c +++ b/ch347_spi.c @@ -51,6 +51,11 @@ int interface; }; +struct device_speeds { + const char *name; + const int speed; +}; + /* TODO: Add support for HID mode */ static const struct dev_entry devs_ch347_spi[] = { {0x1A86, 0x55DB, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, /* CH347T */ @@ -63,6 +68,18 @@ CH347F_IFACE, }; +static const struct device_speeds spispeeds[] = { + {"60M", 0x0}, + {"30M", 0x1}, + {"15M", 0x2}, + {"7.5M", 0x3}, + {"3.75M", 0x4}, + {"1.875M", 0x5}, + {"937.5K", 0x6}, + {"468.75K", 0x7}, + {NULL, 0x0} +}; + static int ch347_spi_shutdown(void *data) { struct ch347_spi_data *ch347_data = data; @@ -332,9 +349,24 @@ (desc.bcdDevice >> 4) & 0x000F, (desc.bcdDevice >> 0) & 0x000F); - /* TODO: add programmer cfg for things like CS pin and divisor */ - if (ch347_spi_config(ch347_data, 2) < 0) + /* TODO: set CH347 clock division */ + arg = extract_programmer_param_str(cfg, "spispeed"); + if (arg) { + for (index = 0; spispeeds[index].name; index++) { + if (!strncasecmp(spispeeds[index].name, arg, strlen(spispeeds[index].name))) { + spispeed = spispeeds[index].speed; + break; + } + } + } + if (!spispeeds[index].name || !arg) + msg_perr("Invalid SPI speed, using defaul(60M clock spi).\n"); + free(arg); + if (ch347_spi_config(ch347_data, spispeed) < 0) { goto error_exit; + } else { + msg_pinfo("CH347 SPI clock set to %s.\n", spispeeds[index].name); + } return register_spi_master(&spi_master_ch347_spi, ch347_data); @@ -348,4 +380,4 @@ .type = USB, .devs.dev = devs_ch347_spi, .init = ch347_spi_init, -}; +}; \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 1 Gerrit-Owner: ZhiYuanNJ

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[L] Change in flashrom[main]: doc: Convert ME and Intel docs
by David Hendricks (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev. David Hendricks has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/82649?usp=email ) Change subject: doc: Convert ME and Intel docs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File doc/user_docs/management_engine.rst: PS1: Does the coding style guidelines apply to documentation as well? We might just need to re-flow this doc to fit in 80 or 112 columns, except the URLs of course. In either case, it's probably best to copy this over from the wiki as closely as possible first and then make formatting changes in a follow-up. -- To view, visit https://review.coreboot.org/c/flashrom/+/82649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I79af5674f3af9ca880e89becd6a272a2cf8ed599 Gerrit-Change-Number: 82649 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 05:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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