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Change subject: hwaccess: fix build on non-x86 targets
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
The hwaccess_x86 files should only get compiled on x86 platforms. So as the code which requires it.
The Makefile handles this already correct and the bug is in the meson script. https://review.coreboot.org/c/flashrom/+/61198 fixes this for meson.
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Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61198 )
Change subject: meson: build hwaccess only on x86
......................................................................
meson: build hwaccess only on x86
Throw an error if an user tries to build a programmer which requires
hwaccess on nox-x86 platforms.
Change-Id: Iafabe8b4b2a95697773a739501dfc62d880d3f6d
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M meson.build
1 file changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/61198/1
diff --git a/meson.build b/meson.build
index 66f6985..e76aef8 100644
--- a/meson.build
+++ b/meson.build
@@ -346,12 +346,16 @@
# raw memory, MSR or PCI port I/O access
if need_raw_access
- srcs += 'hwaccess.c'
- srcs += 'hwaccess_x86_io.c'
- srcs += 'hwaccess_x86_msr.c'
- srcs += 'hwaccess_physmap.c'
- cargs += '-DNEED_RAW_ACCESS=1'
- cargs += '-D__FLASHROM_HAVE_OUTB__=1'
+ if host_machine.cpu_family() in ['x86', 'x86_64']
+ srcs += 'hwaccess.c'
+ srcs += 'hwaccess_x86_io.c'
+ srcs += 'hwaccess_x86_msr.c'
+ srcs += 'hwaccess_physmap.c'
+ cargs += '-DNEED_RAW_ACCESS=1'
+ cargs += '-D__FLASHROM_HAVE_OUTB__=1'
+ else
+ error('RAW access is not available on non-x86 platforms. Disable the programmer which need it. Use meson build -Dpciutils=false -Dconfig_rayer_spi=false')
+ endif
endif
# raw serial IO
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Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61197 )
Change subject: meson: replace target_machine by host_machine
......................................................................
meson: replace target_machine by host_machine
The target_machine object is only used for compiling compilers. The
host_machine onject has the description of the execution environment of
the build binary.
https://mesonbuild.com/Cross-compilation.html
Change-Id: I4a32c73052c3707607738c72256fb4366a2bf8ce
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M meson.build
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/61197/1
diff --git a/meson.build b/meson.build
index b2e2d72..66f6985 100644
--- a/meson.build
+++ b/meson.build
@@ -225,7 +225,7 @@
srcs += 'chipset_enable.c'
srcs += 'internal.c'
srcs += 'processor_enable.c'
- if target_machine.cpu_family() == 'x86' or target_machine.cpu_family() == 'x86_64'
+ if host_machine.cpu_family() == 'x86' or host_machine.cpu_family() == 'x86_64'
srcs += 'amd_imc.c'
srcs += 'dmi.c'
srcs += 'ichspi.c'
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61194 )
Change subject: hwaccess: fix build on non-x86 targets
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61194/comment/46d96fb6_d739558d
PS1, Line 22: Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e
Missing Signed-off-by line?
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Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61194 )
Change subject: hwaccess: fix build on non-x86 targets
......................................................................
hwaccess: fix build on non-x86 targets
The changes to hwaccess in https://review.coreboot.org/c/flashrom/+/60110
cause build failure on non-x86 systems because:
* a new include file pulls in <sys/io.h> which only exists on x86 but
the header may be used on other platforms
* the new rget_io_perms function only works on x86
This change makes sys/io.h and rget_io_perms implementation only be
included when building for x86 targets, which fixes the build on ARM.
BUG=None
TEST=meson build succeeds for both x86 and ARM targets
Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e
---
M hwaccess_x86_io.c
M hwaccess_x86_io.h
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/61194/1
diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c
index 3152bfe..7eee02a 100644
--- a/hwaccess_x86_io.c
+++ b/hwaccess_x86_io.c
@@ -33,7 +33,7 @@
int io_fd;
#endif
-#if !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
+#if defined(__i386__) || defined(__x86_64__) && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
static int release_io_perms(void *p)
{
#if defined (__sun)
@@ -79,7 +79,7 @@
#else
/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
-/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
+/* PCI port I/O support is unimplemented on non-x86 platforms. */
int rget_io_perms(void)
{
return 0;
diff --git a/hwaccess_x86_io.h b/hwaccess_x86_io.h
index 0d16fdd..5cf151d 100644
--- a/hwaccess_x86_io.h
+++ b/hwaccess_x86_io.h
@@ -25,7 +25,7 @@
* that a Linux system's libc has a suitable sys/io.h or (on non-Linux) we depend on glibc to offer it. */
#if defined(__ANDROID__)
#include <sys/glibc-syscalls.h>
-#elif defined(__linux__) || defined(__GLIBC__)
+#elif (defined(__i386__) || defined(__x86_64__)) && (defined(__linux__) || defined(__GLIBC__))
#include <sys/io.h>
#endif
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59742 )
Change subject: tests: Upgrade linux_spi test to run probe lifecycle
......................................................................
Patch Set 4:
(2 comments)
This change is ready for review.
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59742/comment/9ec1c5db_a45d242e
PS2, Line 336: W25Q128.V
> Thank you so much for finding the problem! I missed the elephant in the room, forgot about caching I […]
I fixed my epic fail :) I only have a question about spidev include (I added another comment).
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59742/comment/d61d5041_72f0f817
PS4, Line 18: #include <linux/spi/spidev.h>
This include seems inevitable... is it ok? Do I need to guard it with anything? (like CONFIG_LINUX_SPI for example)
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Change subject: tests: test write protection
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
Sergii, there is a change happening at the moment: converting everything to call libflashrom API, and everything includes tests. Your tests are calling do_erase, so you need to update them as well. Good news: it will be really easy, and here is an example CB:61137
No rush, you can do at convenient time. Your chain will go chronologically after write-protect chain anyway.
Thank you!
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Hello build bot (Jenkins), Nico Huber, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/60230
to look at the new patch set (#5).
Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
spi25_statusreg.c: add SR3 read/write support
Adds support for reading and writing the third status register, which
needs to be enabled per chip.
Extended WRSR doesn't cover SR3, so only one feature flag is added.
Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/60230/5
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#18).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 74 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/18
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] tests: add tests for OTP regions
......................................................................
[RFC][OTP] tests: add tests for OTP regions
There are two sets of tests targeting two new dummyflasher chips that provide
two kinds of OTP.
Change-Id: I4ff584395367dfd52db89332d8e45d7e865276e1
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
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---
A tests/chip_otp.c
M tests/meson.build
M tests/tests.c
M tests/tests.h
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