August 2024 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: libflashrom.map: Add missing symbols
by Edward O'Callaghan (Code Review) 07 Apr '25

07 Apr '25

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38993 ) Change subject: libflashrom.map: Add missing symbols ...................................................................... libflashrom.map: Add missing symbols The following symbols were missing at link-time from libflashrom: supported_flash_chips; supported_boards; supported_chipsets; Change-Id: I299928d62788c0abfe7f6cdd3e8ad8be0c49e45e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M libflashrom.map 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/38993/1 diff --git a/libflashrom.map b/libflashrom.map index d6dd24d..9430775 100644 --- a/libflashrom.map +++ b/libflashrom.map @@ -25,6 +25,9 @@ flashrom_set_log_callback; flashrom_shutdown; flashrom_supported_programmers; + flashrom_supported_flash_chips; + flashrom_supported_boards; + flashrom_supported_chipsets; flashrom_system_info; flashrom_version_info; local: *; -- To view, visit https://review.coreboot.org/c/flashrom/+/38993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I299928d62788c0abfe7f6cdd3e8ad8be0c49e45e Gerrit-Change-Number: 38993 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: tests/: Add programmer enumerate correspondence test
by Edward O'Callaghan (Code Review) 21 Sep '24

21 Sep '24

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47356 ) Change subject: tests/: Add programmer enumerate correspondence test ...................................................................... tests/: Add programmer enumerate correspondence test The enumerate defines within programmer.h must be aligned with the programmer dispatch table within flashrom.c. The following unit-tests tries to improve coverage here to avoid issues like we saw when ENE and MEC1308 were upstreamed. BUG=none BRANCH=none TEST=meson test Change-Id: I13efc4561f743edf51326d4b408be8715b630377 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M tests/flashrom.c M tests/tests.c M tests/tests.h 3 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/47356/1 diff --git a/tests/flashrom.c b/tests/flashrom.c index 50464dd..9180922 100644 --- a/tests/flashrom.c +++ b/tests/flashrom.c @@ -15,6 +15,47 @@ #include <include/test.h> +/* must be before programmer.h include */ +#define CONFIG_INTERNAL 1 +#define CONFIG_DUMMY 1 +#define CONFIG_MEC1308 1 +#define CONFIG_NIC3COM 1 +#define CONFIG_NICREALTEK 1 +#define CONFIG_NICNATSEMI 1 +#define CONFIG_GFXNVIDIA 1 +#define CONFIG_RAIDEN 1 +#define CONFIG_DRKAISER 1 +#define CONFIG_SATASII 1 +#define CONFIG_ATAHPT 1 +#define CONFIG_ATAVIA 1 +#define CONFIG_ATAPROMISE 1 +#define CONFIG_IT8212 1 +#define CONFIG_FT2232_SPI 1 +#define CONFIG_SERPROG 1 +#define CONFIG_BUSPIRATE_SPI 1 +#define CONFIG_DEDIPROG 1 +#define CONFIG_DEVELOPERBOX_SPI 1 +#define CONFIG_ENE_LPC 1 +#define CONFIG_RAYER_SPI 1 +#define CONFIG_PONY_SPI 1 +#define CONFIG_NICINTEL 1 +#define CONFIG_NICINTEL_SPI 1 +#define CONFIG_NICINTEL_EEPROM 1 +#define CONFIG_OGP_SPI 1 +#define CONFIG_SATAMV 1 +#define CONFIG_LINUX_MTD 1 +#define CONFIG_LINUX_SPI 1 +#define CONFIG_LSPCON_I2C_SPI 1 +#define CONFIG_REALTEK_MST_I2C_SPI 1 +#define CONFIG_USBBLASTER_SPI 1 +#define CONFIG_MSTARDDC_SPI 1 +#define CONFIG_PICKIT2_SPI 1 +#define CONFIG_CH341A_SPI 1 +#define CONFIG_DIGILENT_SPI 1 +#define CONFIG_JLINK_SPI 1 +#define CONFIG_NI845X_SPI 1 +#define CONFIG_STLINKV3_SPI 1 + #include "programmer.h" void flashbuses_to_text_test_success(void **state) @@ -49,3 +90,54 @@ bustype = BUS_NONE; assert_string_equal(flashbuses_to_text(bustype), "None"); } + +void validate_prog_enumerates_test_success(void **state) +{ + (void) state; /* unused */ + + enum programmer prog = PROGRAMMER_INTERNAL; + const char *prog_names[] = { + "internal", + "dummy", + "mec1308", + "nic3com", + "nicrealtek", + "nicnatsemi", + "gfxnvidia", + "raiden_debug", + "drkaiser", + "satasii", + "atahpt", + "atavia", + "atapromise", + "it8212", + "ft2232_spi", + "serprog", + "buspirate_spi", + "dediprog", + "developerbox", + "ene_lpc", + "rayer_spi", + "pony_spi", + "nicintel", + "nicintel_spi", + "nicintel_eeprom", + "ogp_spi", + "satamv", + "linux_mtd", + "linux_spi", + "lspcon_i2c_spi", + "realtek_mst_i2c_spi", + "usbblaster_spi", + "mstarddc_spi", + "pickit2_spi", + "ch341a_spi", + "digilent_spi", + "jlink_spi", + "ni845x_spi", + "stlinkv3_spi", + }; + for (; prog < PROGRAMMER_INVALID; prog++) { + assert_string_equal(programmer_table[prog].name, prog_names[prog]); + } +} diff --git a/tests/tests.c b/tests/tests.c index 3124607..d2a22a5 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -46,6 +46,7 @@ const struct CMUnitTest flashrom_tests[] = { cmocka_unit_test(flashbuses_to_text_test_success), + cmocka_unit_test(validate_prog_enumerates_test_success), }; ret |= cmocka_run_group_tests_name("flashrom.c tests", flashrom_tests, NULL, NULL); diff --git a/tests/tests.h b/tests/tests.h index cb905fd..89fc7fa 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -27,6 +27,7 @@ /* flashrom.c */ void flashbuses_to_text_test_success(void **state); +void validate_prog_enumerates_test_success(void **state); /* spi25.c */ void spi_write_enable_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/47356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13efc4561f743edf51326d4b408be8715b630377 Gerrit-Change-Number: 47356 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 10:03:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > All good in the code, but you will need to rebase this patch on the top of main branch. […] I rebased the patch -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 30 Aug 2024 08:28:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has uploaded a new patch set (#3) to the change originally created by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84083/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 30 Aug '24

30 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has uploaded a new patch set (#2) to the change originally created by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Anastasia Klimchuk, Verified+1 by build bot (Jenkins) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... flashchips: add GD25B512MF and GD25R512MF GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-0… Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84083/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... ch347_spi: Add spi clock frequency selection CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use -p ch347_spi:spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <871238103(a)qq.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82776 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ch347_spi.c M doc/classic_cli_manpage.rst 2 files changed, 46 insertions(+), 5 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/ch347_spi.c b/ch347_spi.c index 21dcabb..34f2741 100644 --- a/ch347_spi.c +++ b/ch347_spi.c @@ -51,6 +51,11 @@ int interface; }; +struct device_speeds { + const char *name; + const int divisor; +}; + /* TODO: Add support for HID mode */ static const struct dev_entry devs_ch347_spi[] = { {0x1A86, 0x55DB, OK, "QinHeng Electronics", "USB To UART+SPI+I2C"}, /* CH347T */ @@ -63,6 +68,18 @@ CH347F_IFACE, }; +static const struct device_speeds spispeeds[] = { + {"60M", 0}, + {"30M", 1}, + {"15M", 2}, + {"7.5M", 3}, + {"3.75M", 4}, + {"1.875M", 5}, + {"937.5K", 6}, + {"468.75K", 7}, + {NULL, 0} +}; + static int ch347_spi_shutdown(void *data) { struct ch347_spi_data *ch347_data = data; @@ -266,9 +283,11 @@ /* Largely copied from ch341a_spi.c */ static int ch347_spi_init(const struct programmer_cfg *cfg) { + char *arg; uint16_t vid = devs_ch347_spi[0].vendor_id; uint16_t pid = 0; int index = 0; + int speed_index = 2; struct ch347_spi_data *ch347_data = calloc(1, sizeof(*ch347_data)); if (!ch347_data) { msg_perr("Could not allocate space for SPI data\n"); @@ -332,9 +351,25 @@ (desc.bcdDevice >> 4) & 0x000F, (desc.bcdDevice >> 0) & 0x000F); - /* TODO: add programmer cfg for things like CS pin and divisor */ - if (ch347_spi_config(ch347_data, 2) < 0) + /* set CH347 clock division */ + arg = extract_programmer_param_str(cfg, "spispeed"); + if (arg) { + for (speed_index = 0; spispeeds[speed_index].name; speed_index++) { + if (!strncasecmp(spispeeds[speed_index].name, arg, strlen(spispeeds[speed_index].name))) { + break; + } + } + } + if (!spispeeds[speed_index].name || !arg) { + msg_perr("Unknown value of spispeed parameter, using default 15MHz clock spi.\n"); + speed_index = 2; + } + free(arg); + if (ch347_spi_config(ch347_data, spispeeds[speed_index].divisor) < 0) { goto error_exit; + } else { + msg_pinfo("CH347 SPI clock set to %sHz.\n", spispeeds[speed_index].name); + } return register_spi_master(&spi_master_ch347_spi, ch347_data); @@ -348,4 +383,4 @@ .type = USB, .devs.dev = devs_ch347_spi, .init = ch347_spi_init, -}; +}; \ No newline at end of file diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst index 932f4c9..e2ce684 100644 --- a/doc/classic_cli_manpage.rst +++ b/doc/classic_cli_manpage.rst @@ -1035,8 +1035,14 @@ ch347_spi programmer ^^^^^^^^^^^^^^^^^^^^ -The WCH CH347 programmer does not currently support any parameters. SPI frequency is fixed at 2 MHz, and CS0 is used -as per the device. +An optional ``spispeed`` parameter could be used to specify the SPI speed. This parameter is available for the CH347T and CH347F device. +The default SPI speed is 15MHz if no value is specified. +Syntax is:: + + flashrom -p ch347_spi:spispeed=value + +where ``value`` can be ``60M``, ``30M``, ``15M``, ``7.5M``, ``3.75M``, ``1.875M``, ``937.5K``, ``468.75K``. + ni845x_spi programmer ^^^^^^^^^^^^^^^^^^^^^ -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 15 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: add GD25B512MF and GD25R512MF
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84083?usp=email ) Change subject: flashchips: add GD25B512MF and GD25R512MF ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: All good in the code, but you will need to rebase this patch on the top of main branch. It says "merge conflict", but I think there is no actual conflict. It's just that the adjacent lines, just before in the same file, were submitted in the other patch earlier. Tell me if rebasing won't work, I will have a look. -- To view, visit https://review.coreboot.org/c/flashrom/+/84083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Gerrit-Change-Number: 84083 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 29 Aug 2024 02:44:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Anastasia Klimchuk (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Peter Marheine, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/81608?usp=email ) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 02:19:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: reduce DELAY_MINIMUM_SLEEP_US to 100 by default
by Peter Marheine (Code Review) 29 Aug '24

29 Aug '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Peter Marheine has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/81608?usp=email ) Change subject: reduce DELAY_MINIMUM_SLEEP_US to 100 by default ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Rebased since we no longer have a Makefile. I think this is good to go now. -- To view, visit https://review.coreboot.org/c/flashrom/+/81608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Gerrit-Change-Number: 81608 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Aug 2024 00:02:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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