April 2023 - flashrom-gerrit - mail.coreboot.org

[M] Change in flashrom[master]: internal: Move laptop_ok into board_cfg
by Edward O'Callaghan (Code Review) April 2, 2023

April 2, 2023

Attention is currently required from: Sam McNally, Thomas Heijligen, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73456 ) Change subject: internal: Move laptop_ok into board_cfg ...................................................................... Patch Set 5: (1 comment) File internal.c: https://review.coreboot.org/c/flashrom/+/73456/comment/f71b4a57_e8d297e0 PS3, Line 108: struct > const Done -- To view, visit https://review.coreboot.org/c/flashrom/+/73456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Gerrit-Change-Number: 73456 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Apr 2023 08:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sam McNally <sammc(a)google.com> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: board_enable.c: Avoid excessive forward declarations
by Edward O'Callaghan (Code Review) April 2, 2023

April 2, 2023

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74163 ) Change subject: board_enable.c: Avoid excessive forward declarations ...................................................................... board_enable.c: Avoid excessive forward declarations Dispense with unnecessary C89'isms make the code dramaticaly shorter and to the point. Change-Id: I5d416a023c17568c6275426edc1edb77268ea331 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c 1 file changed, 85 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/74163/1 diff --git a/board_enable.c b/board_enable.c index d9af44e..795d0f3 100644 --- a/board_enable.c +++ b/board_enable.c @@ -64,20 +64,16 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) { - uint8_t tmp; - OUTB(reg, port); - tmp = INB(port + 1) & ~mask; + uint8_t tmp = INB(port + 1) & ~mask; OUTB(tmp | (data & mask), port + 1); } /* Winbond W83697 documentation indicates that the index register has to be written for each access. */ static void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) { - uint8_t tmp; - OUTB(reg, port); - tmp = INB(port + 1) & ~mask; + uint8_t tmp = INB(port + 1) & ~mask; OUTB(reg, port); OUTB(tmp | (data & mask), port + 1); } @@ -116,10 +112,8 @@ */ static int fdc37b787_gpio50_raise(uint16_t port) { - uint8_t id, val; - OUTB(0x55, port); /* enter conf mode */ - id = sio_read(port, 0x20); + uint8_t id = sio_read(port, 0x20); if (id != 0x44) { msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id); OUTB(0xAA, port); /* leave conf mode */ @@ -128,9 +122,8 @@ sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */ - val = sio_read(port, 0xC8); /* GP50 */ - if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ - { + uint8_t val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) { /* output, no invert, GPIO */ msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val); OUTB(0xAA, port); return -1; @@ -252,17 +245,13 @@ */ static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port) { - uint16_t hwmport; - uint16_t hwm_vendorid; - uint8_t hwm_deviceid; - sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */ if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) { msg_pinfo("W836xx hardware monitor disabled or does not exist.\n"); return 0; } /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */ - hwmport = sio_read(sio_port, 0x60) << 8; + uint16_t hwmport = sio_read(sio_port, 0x60) << 8; hwmport |= sio_read(sio_port, 0x61); /* HWM address register = HWM base address + 5. */ hwmport += 5; @@ -275,7 +264,7 @@ /* Set HBACS=1. */ sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80); /* Read upper byte of vendor ID. */ - hwm_vendorid = sio_read(hwmport, 0x4f) << 8; + uint16_t hwm_vendorid = sio_read(hwmport, 0x4f) << 8; /* Set HBACS=0. */ sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80); /* Read lower byte of vendor ID. */ @@ -288,24 +277,22 @@ /* Set Bank=0. */ sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07); /* Read "chip" ID. We call this one the device ID. */ - hwm_deviceid = sio_read(hwmport, 0x58); + uint8_t hwm_deviceid = sio_read(hwmport, 0x58); return hwm_deviceid; } void probe_superio_winbond(void) { - struct superio s = {0}; uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0}; - uint16_t *i = winbond_ports; - uint8_t model; uint8_t tmp; + struct superio s = {0}; s.vendor = SUPERIO_VENDOR_WINBOND; - for (; *i; i++) { + for (uint16_t *i = winbond_ports; *i; i++) { s.port = *i; /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */ w836xx_ext_enter(s.port); - model = sio_read(s.port, 0x20); + uint8_t model = sio_read(s.port, 0x20); /* No response, no point leaving the config mode. */ if (model == 0xff) continue; @@ -373,18 +360,14 @@ } w836xx_ext_leave(s.port); } - return; } static const struct winbond_chip *winbond_superio_chipdef(void) { - int i; - unsigned int j; - - for (i = 0; i < superio_count; i++) { + for (int i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_WINBOND) continue; - for (j = 0; j < ARRAY_SIZE(winbond_chips); j++) + for (unsigned int j = 0; j < ARRAY_SIZE(winbond_chips); j++) if (winbond_chips[j].device_id == superios[i].model) return &winbond_chips[j]; } @@ -399,12 +382,10 @@ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, int pin, int raise) { - const struct winbond_chip *chip = NULL; - const struct winbond_port *gpio; int port = pin / 10; int bit = pin % 10; - chip = winbond_superio_chipdef(); + const struct winbond_chip *chip = winbond_superio_chipdef(); if (!chip) { msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; @@ -420,7 +401,7 @@ return -1; } - gpio = &chip->port[port - 1]; + const struct winbond_port *gpio = &chip->port[port - 1]; if (gpio->ldn == 0) { msg_perr("\nERROR: GPIO%d is not supported yet on this" @@ -603,14 +584,13 @@ */ int it8705f_write_enable(uint8_t port) { - uint8_t tmp; int ret = 0; if (!(internal_buses_supported & BUS_PARALLEL)) return 1; enter_conf_mode_ite(port); - tmp = sio_read(port, 0x24); + uint8_t tmp = sio_read(port, 0x24); /* Check if at least one flash segment is enabled. */ if (tmp & 0xf0) { /* The IT8705F will respond to LPC cycles and translate them. */ @@ -697,12 +677,10 @@ */ static int it8707f_write_enable(uint8_t port) { - uint8_t tmp; - w836xx_ext_enter(port); /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */ - tmp = sio_read(port, 0x23); + uint8_t tmp = sio_read(port, 0x23); tmp |= (1 << 3); sio_write(port, 0x23, tmp); @@ -738,15 +716,13 @@ static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; int gpio_pin = gpio % 8; - uint16_t baseport; - uint8_t id, val; if (gpio_bank > 4) { msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; } - id = sio_read(0x2E, 0x20); + uint8_t id = sio_read(0x2E, 0x20); if (id != chipid) { msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); @@ -754,7 +730,7 @@ } sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */ - baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + uint16_t baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { msg_perr("PC87360: invalid GPIO base address %04x\n", baseport); @@ -764,7 +740,7 @@ sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */ - val = INB(baseport + bankbase[gpio_bank]); + uint8_t val = INB(baseport + bankbase[gpio_bank]); if (raise) val |= 1 << gpio_pin; else @@ -779,11 +755,9 @@ */ static int via_vt823x_gpio_set(uint8_t gpio, int raise) { - struct pci_dev *dev; - uint16_t base; - uint8_t val, bit, offset; + uint8_t val; - dev = pcidev_find_vendorclass(0x1106, 0x0601); + struct pci_dev *dev = pcidev_find_vendorclass(0x1106, 0x0601); switch (dev->device_id) { case 0x3177: /* VT8235 */ case 0x3227: /* VT8237/VT8237R */ @@ -815,10 +789,10 @@ } /* We need the I/O Base Address for this board's flash enable. */ - base = pci_read_word(dev, 0x88) & 0xff80; + uint16_t base = pci_read_word(dev, 0x88) & 0xff80; - offset = 0x4C + gpio / 8; - bit = 0x01 << (gpio % 8); + uint8_t offset = 0x4C + gpio / 8; + uint8_t bit = 0x01 << (gpio % 8); val = INB(base + offset); if (raise) @@ -870,9 +844,7 @@ */ static int board_msi_kt4v(struct board_cfg *cfg) { - int ret; - - ret = via_vt823x_gpio_set(12, 1); + int ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E); return ret; @@ -890,17 +862,14 @@ /* * Find where the SMBus host is. ASUS sets it to 0xE800; coreboot sets it to 0x0F00. */ - struct pci_dev *dev; - uint16_t smbba; - uint8_t b; - dev = pcidev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */ + struct pci_dev *dev = pcidev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); return -1; } - smbba = pci_read_word(dev, 0x90) & 0xfff0; + uint16_t smbba = pci_read_word(dev, 0x90) & 0xfff0; OUTB(0xFF, smbba); /* Clear previous SMBus status. */ OUTB(0x48 << 1, smbba + 4); @@ -909,7 +878,7 @@ OUTB(0x48, smbba + 2); /* Wait until SMBus transaction is complete. */ - b = 0x1; + uint8_t b = 0x1; while (b & 0x01) { INB(0x80); b = INB(smbba); @@ -1043,16 +1012,13 @@ */ static int board_ecs_geforce6100sm_m(struct board_cfg *cfg) { - struct pci_dev *dev; - uint32_t tmp; - - dev = pcidev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */ + struct pci_dev *dev = pcidev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */ if (!dev) { msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n"); return -1; } - tmp = pci_read_byte(dev, 0xE0); + uint32_t tmp = pci_read_byte(dev, 0xE0); tmp &= ~(1 << 3); pci_write_byte(dev, 0xE0, tmp); @@ -1064,17 +1030,13 @@ */ static int nvidia_mcp_gpio_set(int gpio, int raise) { - struct pci_dev *dev; - uint16_t base, devclass; - uint8_t tmp; - if ((gpio < 0) || (gpio >= 0x40)) { msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } /* Check for the ISA bridge first. */ - dev = pcidev_find_vendorclass(0x10DE, 0x0601); + struct pci_dev *dev = pcidev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ @@ -1100,7 +1062,7 @@ msg_perr("MCP SMBus controller could not be found\n"); return -1; } - devclass = pci_read_word(dev, PCI_CLASS_DEVICE); + uint16_t devclass = pci_read_word(dev, PCI_CLASS_DEVICE); if (devclass != 0x0C05) { msg_perr("Unexpected device class %04x for SMBus" " controller\n", devclass); @@ -1112,10 +1074,10 @@ return -1; } - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + uint16_t base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ base += 0xC0; - tmp = INB(base + gpio); + uint8_t tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) @@ -1265,26 +1227,21 @@ */ static int board_sun_ultra_40_m2(struct board_cfg *cfg) { - int ret; - uint8_t reg; - uint16_t base; - struct pci_dev *dev; - - ret = nvidia_mcp_gpio4_lower(cfg); + int ret = nvidia_mcp_gpio4_lower(cfg); if (ret) return ret; - dev = pcidev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + struct pci_dev *dev = pcidev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ if (!dev) { msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); return -1; } - base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + uint16_t base = pci_read_word(dev, 0xb4); /* some IO BAR? */ if (!base) return -1; - reg = INB(base + 0x4b); + uint8_t reg = INB(base + 0x4b); reg |= 0x10; OUTB(reg, base + 0x4b); @@ -1307,14 +1264,13 @@ #define DBE6x_BOOT_LOC_FLASH 2 #define DBE6x_BOOT_LOC_FWHUB 3 - msr_t msr; unsigned long boot_loc; /* Geode only has a single core */ if (msr_setup(0)) return -1; - msr = msr_read(DBE6x_MSR_DIVIL_BALL_OPTS); + msr_t msr = msr_read(DBE6x_MSR_DIVIL_BALL_OPTS); if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) == (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT)) @@ -1341,16 +1297,13 @@ */ static int amd_sbxxx_gpio9_raise(struct board_cfg *cfg) { - struct pci_dev *dev; - uint32_t reg; - - dev = pcidev_find(0x1002, 0x4372); /* AMD SMBus controller */ + struct pci_dev *dev = pcidev_find(0x1002, 0x4372); /* AMD SMBus controller */ if (!dev) { msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); return -1; } - reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ + uint32_t reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ /* enable output (0: enable, 1: tristate): GPIO9 output enable is at bit 5 in 0xA9 */ reg &= ~((uint32_t)1<<(8+5)); @@ -1367,10 +1320,6 @@ */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) { - unsigned int gpo_byte, gpo_bit; - struct pci_dev *dev; - uint32_t tmp, base; - /* GPO{0,8,27,28,30} are always available. */ static const uint32_t nonmuxed_gpos = 0x58000101; @@ -1408,7 +1357,7 @@ {0} }; - dev = pcidev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ + struct pci_dev *dev = pcidev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ if (!dev) { msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); return -1; @@ -1434,11 +1383,11 @@ } /* PM IO base */ - base = pci_read_long(dev, 0x40) & 0x0000FFC0; + uint32_t base = pci_read_long(dev, 0x40) & 0x0000FFC0; - gpo_byte = gpo >> 3; - gpo_bit = gpo & 7; - tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ + unsigned int gpo_byte = gpo >> 3; + unsigned int gpo_bit = gpo & 7; + uint32_t tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ if (raise) tmp |= 0x01 << gpo_bit; else @@ -1550,13 +1499,11 @@ {0, 0, 0, 0, 0} /* end marker */ }; - struct pci_dev *dev; - uint16_t base; uint32_t tmp; int i, allowed; /* First, look for a known LPC bridge */ - dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */ + struct pci_dev *dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */ if (!dev) { msg_perr("\nERROR: No known Intel LPC bridge found.\n"); return -1; @@ -1576,7 +1523,7 @@ * strapped to zero. From some mobile ICH9 version on, this becomes * 6:1. The mask below catches all. */ - base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; + uint16_t base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; /* Check whether the line is allowed. */ if (gpio < 32) @@ -1808,8 +1755,7 @@ */ static int board_hp_vl400(struct board_cfg *cfg) { - int ret; - ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ + int ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ if (!ret) ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ if (!ret) @@ -1902,10 +1848,8 @@ */ static int board_acorp_6a815epd(struct board_cfg *cfg) { - int ret; - /* Lower Blocks Lock -- pin 7 of PLCC32 */ - ret = intel_ich_gpio_set(22, 1); + int ret = intel_ich_gpio_set(22, 1); if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ ret = intel_ich_gpio_set(23, 1); @@ -1918,9 +1862,7 @@ */ static int board_kontron_986lcd_m(struct board_cfg *cfg) { - int ret; - - ret = intel_ich_gpio_set(34, 1); /* #TBL */ + int ret = intel_ich_gpio_set(34, 1); /* #TBL */ if (!ret) ret = intel_ich_gpio_set(35, 1); /* #WP */ @@ -1933,11 +1875,8 @@ */ static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; - uint32_t base, tmp; - /* VT82C686 power management */ - dev = pcidev_find(0x1106, 0x3057); + struct pci_dev *dev = pcidev_find(0x1106, 0x3057); if (!dev) { msg_perr("\nERROR: VT82C686 PM device not found.\n"); return -1; @@ -1947,7 +1886,7 @@ raise ? "Rais" : "Dropp", gpio); /* Select GPO function on multiplexed pins. */ - tmp = pci_read_byte(dev, 0x54); + uint32_t tmp = pci_read_byte(dev, 0x54); switch (gpio) { case 0: tmp &= ~0x03; @@ -1965,7 +1904,7 @@ pci_write_byte(dev, 0x54, tmp); /* PM IO base */ - base = pci_read_long(dev, 0x48) & 0x0000FF00; + uint32_t base = pci_read_long(dev, 0x48) & 0x0000FF00; /* Drop GPO0 */ tmp = INL(base + 0x4C); @@ -2007,17 +1946,14 @@ */ static int sis_gpio0_raise_and_w836xx_memw(struct board_cfg *cfg) { - struct pci_dev *dev; - uint16_t base, temp; - - dev = pcidev_find(0x1039, 0x0962); + struct pci_dev *dev = pcidev_find(0x1039, 0x0962); if (!dev) { msg_perr("Expected south bridge not found\n"); return 1; } - base = pci_read_word(dev, 0x74); - temp = INW(base + 0x68); + uint16_t base = pci_read_word(dev, 0x74); + uint16_t temp = INW(base + 0x68); temp &= ~(1 << 0); /* Make pin output? */ OUTW(temp, base + 0x68); @@ -2070,22 +2006,18 @@ */ static int board_mitac_6513wu(struct board_cfg *cfg) { - struct pci_dev *dev; - uint16_t rt_port; - uint8_t val; - - dev = pcidev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ + struct pci_dev *dev = pcidev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ if (!dev) { msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); return -1; } - rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); + uint16_t rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); if (rt_port == 0) return -1; /* Configure the GPIO pin. */ - val = INB(rt_port + 0x33); /* GP30 config */ + uint8_t val = INB(rt_port + 0x33); /* GP30 config */ val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33); @@ -2103,10 +2035,8 @@ */ static int board_abit_av8(struct board_cfg *cfg) { - uint8_t val; - /* Raise GPO pins GP22 & GP23 */ - val = INB(0x404E); + uint8_t val = INB(0x404E); val |= 0xC0; OUTB(val, 0x404E); @@ -2120,12 +2050,9 @@ */ static int it8703f_gpio51_raise(struct board_cfg *cfg) { - uint16_t id, base; - uint8_t tmp; - /* Find the IT8703F. */ w836xx_ext_enter(0x2E); - id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); + uint16_t id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); w836xx_ext_leave(0x2E); if (id != 0x8701) { @@ -2136,7 +2063,7 @@ /* Get the GP567 I/O base. */ w836xx_ext_enter(0x2E); sio_write(0x2E, 0x07, 0x0C); - base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); + uint16_t base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); w836xx_ext_leave(0x2E); if (!base) { @@ -2146,7 +2073,7 @@ } /* Raise GP51. */ - tmp = INB(base); + uint8_t tmp = INB(base); tmp |= 0x02; OUTB(tmp, base); @@ -2160,8 +2087,6 @@ { int allowed, sio; unsigned int port; - uint16_t base, sioport; - uint8_t tmp; /* IT87 GPIO configuration table */ static const struct it87cfg { @@ -2179,19 +2104,19 @@ /* Find the Super I/O in the probed list */ for (sio = 0; sio < superio_count; sio++) { - int i; if (superios[sio].vendor != SUPERIO_VENDOR_ITE) continue; /* Is this device in our list? */ - for (i = 0; it87_gpio_table[i].id; i++) + for (int i = 0; it87_gpio_table[i].id; i++) { if (superios[sio].model == it87_gpio_table[i].id) { cfg = &it87_gpio_table[i]; goto found; } + } } - if (cfg == NULL) { + if (!cfg) { msg_perr("\nERROR: No IT87 Super I/O GPIO configuration " "found.\n"); return -1; @@ -2215,10 +2140,10 @@ } /* Read the Simple I/O Base Address Register */ - sioport = superios[sio].port; + uint16_t sioport = superios[sio].port; enter_conf_mode_ite(sioport); sio_write(sioport, 0x07, 0x07); - base = (sio_read(sioport, cfg->base_reg) << 8) | + uint16_t base = (sio_read(sioport, cfg->base_reg) << 8) | sio_read(sioport, cfg->base_reg + 1); exit_conf_mode_ite(sioport); @@ -2233,7 +2158,7 @@ gpio %= 10; /* set GPIO. */ - tmp = INB(base + port); + uint8_t tmp = INB(base + port); if (raise) tmp |= 1 << gpio; else @@ -2534,8 +2459,7 @@ } int ret = 0; - unsigned int i; - for (i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) { + for (unsigned int i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) { const struct board_match *b = &board_matches[i]; if (b->vendor_name == NULL || b->board_name == NULL) { msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n" -- To view, visit https://review.coreboot.org/c/flashrom/+/74163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5d416a023c17568c6275426edc1edb77268ea331 Gerrit-Change-Number: 74163 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[master]: board_enable.c: Invert branch for readability
by Edward O'Callaghan (Code Review) April 2, 2023

April 2, 2023

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74164 ) Change subject: board_enable.c: Invert branch for readability ...................................................................... board_enable.c: Invert branch for readability Just use a early return for a base condition of the function to aid in removing one layer of logic embedding within a branch. Change-Id: I9bd96d4d077270697c329d7e6cac1d32ed513ed3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c 1 file changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/74164/1 diff --git a/board_enable.c b/board_enable.c index 795d0f3..121b211 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2661,7 +2661,6 @@ bool force_boardenable) { const struct board_match *board = NULL; - int ret = 0; if (vendor && model) { board = board_match_name(vendor, model, false); @@ -2691,16 +2690,17 @@ if (board->max_rom_decode_parallel) max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; - if (board->enable) { - msg_pinfo("Enabling full flash access for board \"%s %s\"... ", - board->vendor_name, board->board_name); + if (!board->enable) + return 0; - ret = board->enable(cfg); - if (ret) - msg_pinfo("FAILED!\n"); - else - msg_pinfo("OK.\n"); - } + msg_pinfo("Enabling full flash access for board \"%s %s\"... ", + board->vendor_name, board->board_name); + + int ret = board->enable(cfg); + if (ret) + msg_pinfo("FAILED!\n"); + else + msg_pinfo("OK.\n"); return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/74164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9bd96d4d077270697c329d7e6cac1d32ed513ed3 Gerrit-Change-Number: 74164 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in flashrom[master]: internal: Move laptop_ok into board_cfg
by Edward O'Callaghan (Code Review) April 2, 2023

April 2, 2023

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Angel Pons. Hello Sam McNally, build bot (Jenkins), Thomas Heijligen, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/73456 to look at the new patch set (#5). Change subject: internal: Move laptop_ok into board_cfg ...................................................................... internal: Move laptop_ok into board_cfg Due to how internal is structured around chipset_flash_enable() entry we need to prepare a crafted programmer_cfg that contains a board_enable substructure with data derived from the board_enable subsystem. While this is certainly not perfection, it does make clear the relationships between board_enable into chipset_flash_enable and subsequently the overall internal programmer initialisation in a RAII fashion at the type level over closure upon global state that is impossible to reason about. Also flip predicate in report_nonwl_laptop_detected() and return early with the trivial base-case. TEST=`$ sudo ./flashrom -p internal --flash-name`. Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M chipset_enable.c M flashrom.c M include/programmer.h M internal.c 5 files changed, 69 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/73456/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/73456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I459215253845c2af73262943ce91a36464e9eb06 Gerrit-Change-Number: 73456 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in flashrom[master]: internal: Move is_laptop into board_cfg
by Edward O'Callaghan (Code Review) April 1, 2023

April 1, 2023

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/73455 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: internal: Move is_laptop into board_cfg ...................................................................... internal: Move is_laptop into board_cfg Change-Id: I24e38e4457299934acdcd70325d0bf0f4b139e5f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73455 Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M board_enable.c M include/programmer.h M internal.c 3 files changed, 21 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved diff --git a/board_enable.c b/board_enable.c index fc21283..f95430a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2282,7 +2282,7 @@ static int p2_not_a_laptop(struct board_cfg *cfg) { /* label this board as not a laptop */ - g_is_laptop = 0; + cfg->is_laptop = 0; msg_pdbg("Laptop detection overridden by P2 board enable.\n"); return 0; } @@ -2292,7 +2292,7 @@ */ static int p2_whitelist_laptop(struct board_cfg *cfg) { - g_is_laptop = 1; + cfg->is_laptop = 1; g_laptop_ok = true; msg_pdbg("Whitelisted laptop detected.\n"); return 0; diff --git a/include/programmer.h b/include/programmer.h index 047f49a..157de2e 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -161,6 +161,7 @@ }; struct board_cfg { + int is_laptop; }; struct board_match { @@ -266,7 +267,6 @@ #endif #if CONFIG_INTERNAL == 1 -extern int g_is_laptop; extern bool g_laptop_ok; extern bool force_boardmismatch; void probe_superio(void); diff --git a/internal.c b/internal.c index c8d0a93..1f0e6ee 100644 --- a/internal.c +++ b/internal.c @@ -27,7 +27,6 @@ #include "hwaccess_x86_io.h" #endif -int g_is_laptop = 0; bool g_laptop_ok = false; bool force_boardmismatch = false; @@ -149,7 +148,7 @@ const char *cb_model = NULL; #endif bool force_boardenable = false; - struct board_cfg bcfg; + struct board_cfg bcfg = {0}; ret = get_params(cfg, &force_boardenable, &force_boardmismatch, @@ -204,9 +203,9 @@ } } - g_is_laptop = 2; /* Assume that we don't know by default. */ + bcfg.is_laptop = 2; /* Assume that we don't know by default. */ - dmi_init(&g_is_laptop); + dmi_init(&bcfg.is_laptop); /* In case Super I/O probing would cause pretty explosions. */ board_handle_before_superio(&bcfg, force_boardenable); @@ -229,7 +228,7 @@ * this isn't a laptop. Board-enables may override this, * non-legacy buses (SPI and opaque atm) are probed anyway. */ - if (g_is_laptop && !(g_laptop_ok || force_laptop || (not_a_laptop && g_is_laptop == 2))) + if (bcfg.is_laptop && !(g_laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2))) internal_buses_supported = BUS_NONE; /* try to enable it. Failure IS an option, since not all motherboards @@ -259,7 +258,7 @@ internal_par_init(internal_buses_supported); /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */ - report_nonwl_laptop_detected(g_is_laptop, g_laptop_ok); + report_nonwl_laptop_detected(bcfg.is_laptop, g_laptop_ok); ret = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/73455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I24e38e4457299934acdcd70325d0bf0f4b139e5f Gerrit-Change-Number: 73455 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in flashrom[master]: board_enables: Allow for prog cfg coupling with board cfg
by Edward O'Callaghan (Code Review) April 1, 2023

April 1, 2023

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/71623 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: board_enables: Allow for prog cfg coupling with board cfg ...................................................................... board_enables: Allow for prog cfg coupling with board cfg Some boards need to configure the programmer in specific ways. For example, a programmer such as internal may need to be configured either as laptop or not type and as such the board enable needs the ability to feed state back into the programmer configuration. Plumb this though by creating a board_cfg structure that can be packed. Change-Id: I7058a693e714a6966a842ae97cc8da7296e63e5e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71623 Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M board_enable.c M include/programmer.h M internal.c M wbsio_spi.c 4 files changed, 115 insertions(+), 89 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved diff --git a/board_enable.c b/board_enable.c index abc8b09..fc21283 100644 --- a/board_enable.c +++ b/board_enable.c @@ -146,7 +146,7 @@ * Suited for: * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 */ -static int fdc37b787_gpio50_raise_3f0(void) +static int fdc37b787_gpio50_raise_3f0(struct board_cfg *cfg) { return fdc37b787_gpio50_raise(0x3f0); } @@ -457,7 +457,7 @@ * - Agami Aruma * - IWILL DK8-HTX */ -static int w83627hf_gpio24_raise_2e(void) +static int w83627hf_gpio24_raise_2e(struct board_cfg *cfg) { return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1); } @@ -468,7 +468,7 @@ * Suited for: * - MSI MS-6577 */ -static int w83627hf_gpio25_raise_2e(void) +static int w83627hf_gpio25_raise_2e(struct board_cfg *cfg) { return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1); } @@ -479,7 +479,7 @@ * Suited for: * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51 */ -static int w83627ehf_gpio22_raise_2e(void) +static int w83627ehf_gpio22_raise_2e(struct board_cfg *cfg) { return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1); } @@ -490,7 +490,7 @@ * Suited for: * - MSI K8T Neo2-F V2.0 */ -static int w83627thf_gpio44_raise_2e(void) +static int w83627thf_gpio44_raise_2e(struct board_cfg *cfg) { return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1); } @@ -501,7 +501,7 @@ * Suited for: * - MSI K8N Neo3 */ -static int w83627thf_gpio44_raise_4e(void) +static int w83627thf_gpio44_raise_4e(struct board_cfg *cfg) { return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1); } @@ -557,7 +557,7 @@ * Suited for: * - Biostar M7VIQ: VIA KM266 + VT8235 */ -static int w83697xx_memw_enable_2e(void) +static int w83697xx_memw_enable_2e(struct board_cfg *cfg) { w83697xx_memw_enable(0x2E); @@ -579,7 +579,7 @@ * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF */ -static int w836xx_memw_enable_2e(void) +static int w836xx_memw_enable_2e(struct board_cfg *cfg) { w836xx_memw_enable(0x2E); @@ -590,7 +590,7 @@ * Suited for: * - Termtek TK-3370 (rev. 2.5b) */ -static int w836xx_memw_enable_4e(void) +static int w836xx_memw_enable_4e(struct board_cfg *cfg) { w836xx_memw_enable(0x4E); @@ -725,7 +725,7 @@ * Suited for: * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F */ -static int it8707f_write_enable_2e(void) +static int it8707f_write_enable_2e(struct board_cfg *cfg) { return it8707f_write_enable(0x2e); } @@ -834,7 +834,7 @@ * Suited for: * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F */ -static int via_vt823x_gpio5_raise(void) +static int via_vt823x_gpio5_raise(struct board_cfg *cfg) { /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ return via_vt823x_gpio_set(5, 1); @@ -844,7 +844,7 @@ * Suited for: * - VIA EPIA EK & N & NL */ -static int via_vt823x_gpio9_raise(void) +static int via_vt823x_gpio9_raise(struct board_cfg *cfg) { return via_vt823x_gpio_set(9, 1); } @@ -856,7 +856,7 @@ * We don't need to do this for EPIA M when using coreboot, GPIO15 is never * lowered there. */ -static int via_vt823x_gpio15_raise(void) +static int via_vt823x_gpio15_raise(struct board_cfg *cfg) { return via_vt823x_gpio_set(15, 1); } @@ -868,7 +868,7 @@ * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ -static int board_msi_kt4v(void) +static int board_msi_kt4v(struct board_cfg *cfg) { int ret; @@ -885,7 +885,7 @@ * We are talking to a proprietary device on SMBus: the AS99127F which does * much more than the Winbond W83781D it tries to be compatible with. */ -static int board_asus_p3b_f(void) +static int board_asus_p3b_f(struct board_cfg *cfg) { /* * Find where the SMBus host is. ASUS sets it to 0xE800; coreboot sets it to 0x0F00. @@ -932,7 +932,7 @@ * We're basically talking to some unknown device on SMBus, my guess * is that it is the Winbond W83781D that lives near the DIP BIOS. */ -static int board_asus_p5a(void) +static int board_asus_p5a(struct board_cfg *cfg) { uint8_t tmp; int i; @@ -1006,7 +1006,7 @@ * * It's not a Super I/O but it uses the same index/data port method. */ -static int board_hp_dl145_g3_enable(void) +static int board_hp_dl145_g3_enable(struct board_cfg *cfg) { /* GPIO 0 reg from PM regs */ /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ @@ -1020,7 +1020,7 @@ * * It's not a Super I/O but it uses the same index/data port method. */ -static int board_hp_dl165_g6_enable(void) +static int board_hp_dl165_g6_enable(struct board_cfg *cfg) { /* Variant of DL145, with slightly different pin placement. */ sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */ @@ -1029,7 +1029,7 @@ return 0; } -static int board_ibm_x3455(void) +static int board_ibm_x3455(struct board_cfg *cfg) { /* Raise GPIO13. */ sio_mask(0xcd6, 0x45, 0x20, 0x20); @@ -1041,7 +1041,7 @@ * Suited for: * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F */ -static int board_ecs_geforce6100sm_m(void) +static int board_ecs_geforce6100sm_m(struct board_cfg *cfg) { struct pci_dev *dev; uint32_t tmp; @@ -1131,7 +1131,7 @@ * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51 * - ASUS M2NBP-VM CSM: NVIDIA MCP51 */ -static int nvidia_mcp_gpio0_raise(void) +static int nvidia_mcp_gpio0_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x00, 1); } @@ -1141,7 +1141,7 @@ * - abit KN8 Ultra: NVIDIA CK804 * - abit KN9 Ultra: NVIDIA MCP55 */ -static int nvidia_mcp_gpio2_lower(void) +static int nvidia_mcp_gpio2_lower(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x02, 0); } @@ -1153,7 +1153,7 @@ * - MSI K8NGM2-L: NVIDIA MCP51 * - MSI K9N SLI: NVIDIA MCP55 */ -static int nvidia_mcp_gpio2_raise(void) +static int nvidia_mcp_gpio2_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x02, 1); } @@ -1162,7 +1162,7 @@ * Suited for: * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X */ -static int nvidia_mcp_gpio4_raise(void) +static int nvidia_mcp_gpio4_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x04, 1); } @@ -1179,7 +1179,7 @@ * b) #TBL is hardwired on that board to a pull-down. It can be * overridden by connecting the two solder points next to F2. */ -static int nvidia_mcp_gpio5_raise(void) +static int nvidia_mcp_gpio5_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x05, 1); } @@ -1188,7 +1188,7 @@ * Suited for: * - abit NF7-S: NVIDIA CK804 */ -static int nvidia_mcp_gpio8_raise(void) +static int nvidia_mcp_gpio8_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x08, 1); } @@ -1198,7 +1198,7 @@ * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8 * - Probably other versions of the GA-K8NS */ -static int nvidia_mcp_gpio0a_raise(void) +static int nvidia_mcp_gpio0a_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x0a, 1); } @@ -1208,7 +1208,7 @@ * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8 */ -static int nvidia_mcp_gpio0c_raise(void) +static int nvidia_mcp_gpio0c_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x0c, 1); } @@ -1217,7 +1217,7 @@ * Suited for: * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51 */ -static int nvidia_mcp_gpio4_lower(void) +static int nvidia_mcp_gpio4_lower(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x04, 0); } @@ -1226,7 +1226,7 @@ * Suited for: * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04 */ -static int nvidia_mcp_gpio10_raise(void) +static int nvidia_mcp_gpio10_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x10, 1); } @@ -1235,7 +1235,7 @@ * Suited for: * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F */ -static int nvidia_mcp_gpio21_raise(void) +static int nvidia_mcp_gpio21_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x21, 0x01); } @@ -1244,7 +1244,7 @@ * Suited for: * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2 */ -static int nvidia_mcp_gpio31_raise(void) +static int nvidia_mcp_gpio31_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x31, 0x01); } @@ -1254,7 +1254,7 @@ * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ -static int nvidia_mcp_gpio3b_raise(void) +static int nvidia_mcp_gpio3b_raise(struct board_cfg *cfg) { return nvidia_mcp_gpio_set(0x3b, 1); } @@ -1263,14 +1263,14 @@ * Suited for: * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 */ -static int board_sun_ultra_40_m2(void) +static int board_sun_ultra_40_m2(struct board_cfg *cfg) { int ret; uint8_t reg; uint16_t base; struct pci_dev *dev; - ret = nvidia_mcp_gpio4_lower(); + ret = nvidia_mcp_gpio4_lower(cfg); if (ret) return ret; @@ -1295,7 +1295,7 @@ * Suited for: * - Artec Group DBE61 and DBE62 */ -static int board_artecgroup_dbe6x(void) +static int board_artecgroup_dbe6x(struct board_cfg *cfg) { #define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015 #define DBE6x_PRI_BOOT_LOC_SHIFT 2 @@ -1339,7 +1339,7 @@ * Datasheet(s) used: * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00 */ -static int amd_sbxxx_gpio9_raise(void) +static int amd_sbxxx_gpio9_raise(struct board_cfg *cfg) { struct pci_dev *dev; uint32_t reg; @@ -1453,7 +1453,7 @@ * - ASUS OPLX-M * - ASUS P2B-N */ -static int intel_piix4_gpo18_lower(void) +static int intel_piix4_gpo18_lower(struct board_cfg *cfg) { return intel_piix4_gpo_set(18, 0); } @@ -1462,7 +1462,7 @@ * Suited for: * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF */ -static int intel_piix4_gpo14_raise(void) +static int intel_piix4_gpo14_raise(struct board_cfg *cfg) { return intel_piix4_gpo_set(14, 1); } @@ -1471,7 +1471,7 @@ * Suited for: * - EPoX EP-BX3 */ -static int intel_piix4_gpo22_raise(void) +static int intel_piix4_gpo22_raise(struct board_cfg *cfg) { return intel_piix4_gpo_set(22, 1); } @@ -1480,7 +1480,7 @@ * Suited for: * - abit BM6 */ -static int intel_piix4_gpo26_lower(void) +static int intel_piix4_gpo26_lower(struct board_cfg *cfg) { return intel_piix4_gpo_set(26, 0); } @@ -1489,7 +1489,7 @@ * Suited for: * - Intel SE440BX-2 */ -static int intel_piix4_gpo27_lower(void) +static int intel_piix4_gpo27_lower(struct board_cfg *cfg) { return intel_piix4_gpo_set(27, 0); } @@ -1498,7 +1498,7 @@ * Suited for: * - Dell OptiPlex GX1 */ -static int intel_piix4_gpo30_lower(void) +static int intel_piix4_gpo30_lower(struct board_cfg *cfg) { return intel_piix4_gpo_set(30, 0); } @@ -1704,7 +1704,7 @@ * - ASUS P5LD2-VM DH * - ASUS P5W DH Deluxe */ -static int intel_ich_gpio16_raise(void) +static int intel_ich_gpio16_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(16, 1); } @@ -1713,7 +1713,7 @@ * Suited for: * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6 */ -static int intel_ich_gpio18_raise(void) +static int intel_ich_gpio18_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(18, 1); } @@ -1722,7 +1722,7 @@ * Suited for: * - MSI MS-7046: LGA775 + 915P + ICH6 */ -static int intel_ich_gpio19_raise(void) +static int intel_ich_gpio19_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(19, 1); } @@ -1732,7 +1732,7 @@ * - ASUS P5BV-R: LGA775 + 3200 + ICH7 * - AOpen i965GMt-LA: Intel Socket479 + 965GM + ICH8M */ -static int intel_ich_gpio20_raise(void) +static int intel_ich_gpio20_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(20, 1); } @@ -1754,7 +1754,7 @@ * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2 * - Samsung Polaris 32: socket478 + 865P + ICH5 */ -static int intel_ich_gpio21_raise(void) +static int intel_ich_gpio21_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(21, 1); } @@ -1766,7 +1766,7 @@ * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH */ -static int intel_ich_gpio22_raise(void) +static int intel_ich_gpio22_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(22, 1); } @@ -1778,7 +1778,7 @@ * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E" * - Epson Endeavor MT7700 */ -static int intel_ich_gpio34_raise(void) +static int intel_ich_gpio34_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(34, 1); } @@ -1788,7 +1788,7 @@ * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ... * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1) */ -static int intel_ich_gpio38_raise(void) +static int intel_ich_gpio38_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(38, 1); } @@ -1797,7 +1797,7 @@ * Suited for: * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M */ -static int intel_ich_gpio43_raise(void) +static int intel_ich_gpio43_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(43, 1); } @@ -1806,7 +1806,7 @@ * Suited for: * - HP Vectra VL400: 815 + ICH + PC87360 */ -static int board_hp_vl400(void) +static int board_hp_vl400(struct board_cfg *cfg) { int ret; ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ @@ -1821,7 +1821,7 @@ * Suited for: * - HP e-Vectra P2706T: 810E + ICH + PC87364 */ -static int board_hp_p2706t(void) +static int board_hp_p2706t(struct board_cfg *cfg) { int ret; ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); @@ -1837,7 +1837,7 @@ * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2 */ -static int intel_ich_gpio23_raise(void) +static int intel_ich_gpio23_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(23, 1); } @@ -1847,7 +1847,7 @@ * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2 */ -static int intel_ich_gpio25_raise(void) +static int intel_ich_gpio25_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(25, 1); } @@ -1856,7 +1856,7 @@ * Suited for: * - IBASE MB899: i945GM + ICH7 */ -static int intel_ich_gpio26_raise(void) +static int intel_ich_gpio26_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(26, 1); } @@ -1869,7 +1869,7 @@ * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4 * - MSI MS-6788-40 (aka 848P Neo-V) */ -static int intel_ich_gpio32_raise(void) +static int intel_ich_gpio32_raise(struct board_cfg *cfg) { return intel_ich_gpio_set(32, 1); } @@ -1878,7 +1878,7 @@ * Suited for: * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF */ -static int board_aopen_i975xa_ydg(void) +static int board_aopen_i975xa_ydg(struct board_cfg *cfg) { int ret; @@ -1900,7 +1900,7 @@ * Suited for: * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2 */ -static int board_acorp_6a815epd(void) +static int board_acorp_6a815epd(struct board_cfg *cfg) { int ret; @@ -1916,7 +1916,7 @@ * Suited for: * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R */ -static int board_kontron_986lcd_m(void) +static int board_kontron_986lcd_m(struct board_cfg *cfg) { int ret; @@ -1983,7 +1983,7 @@ * - abit VT6X4: Pro133x + VT82C686A * - abit VA6: Pro133x + VT82C686A */ -static int via_apollo_gpo4_lower(void) +static int via_apollo_gpo4_lower(struct board_cfg *cfg) { return via_apollo_gpo_set(4, 0); } @@ -1992,7 +1992,7 @@ * Suited for: * - Soyo SY-7VCA: Pro133A + VT82C686 */ -static int via_apollo_gpo0_lower(void) +static int via_apollo_gpo0_lower(struct board_cfg *cfg) { return via_apollo_gpo_set(0, 0); } @@ -2005,7 +2005,7 @@ * - GIGABYTE GA-8SIMLFS 2.0 * - GIGABYTE GA-8SIMLH */ -static int sis_gpio0_raise_and_w836xx_memw(void) +static int sis_gpio0_raise_and_w836xx_memw(struct board_cfg *cfg) { struct pci_dev *dev; uint16_t base, temp; @@ -2068,7 +2068,7 @@ * Disable write protection on the Mitac 6513WU. WP# on the FWH is * connected to GP30 on the Super I/O, and TBL# is always high. */ -static int board_mitac_6513wu(void) +static int board_mitac_6513wu(struct board_cfg *cfg) { struct pci_dev *dev; uint16_t rt_port; @@ -2101,7 +2101,7 @@ * Suited for: * - abit AV8: Socket939 + K8T800Pro + VT8237 */ -static int board_abit_av8(void) +static int board_abit_av8(struct board_cfg *cfg) { uint8_t val; @@ -2118,7 +2118,7 @@ * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F */ -static int it8703f_gpio51_raise(void) +static int it8703f_gpio51_raise(struct board_cfg *cfg) { uint16_t id, base; uint8_t tmp; @@ -2247,7 +2247,7 @@ * Suited for: * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F */ -static int it8712f_gpio12_raise(void) +static int it8712f_gpio12_raise(struct board_cfg *cfg) { return it87_gpio_set(12, 1); } @@ -2257,7 +2257,7 @@ * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F */ -static int it8712f_gpio31_raise(void) +static int it8712f_gpio31_raise(struct board_cfg *cfg) { return it87_gpio_set(32, 1); } @@ -2267,7 +2267,7 @@ * - ASUS P5N-D: NVIDIA MCP51 + IT8718F * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F */ -static int it8718f_gpio63_raise(void) +static int it8718f_gpio63_raise(struct board_cfg *cfg) { return it87_gpio_set(63, 1); } @@ -2279,7 +2279,7 @@ * - Intel D945GCNL * - MSC Q7 Tunnel Creek Module (Q7-TCTC) */ -static int p2_not_a_laptop(void) +static int p2_not_a_laptop(struct board_cfg *cfg) { /* label this board as not a laptop */ g_is_laptop = 0; @@ -2290,7 +2290,7 @@ /* * Suited for all laptops, which are known to *not* have interfering embedded controllers. */ -static int p2_whitelist_laptop(void) +static int p2_whitelist_laptop(struct board_cfg *cfg) { g_is_laptop = 1; g_laptop_ok = true; @@ -2705,7 +2705,8 @@ } /* FIXME: Should this be identical to board_flash_enable? */ -static int board_handle_phase(enum board_match_phase phase, bool force_boardenable) +static int board_handle_phase(struct board_cfg *cfg, + enum board_match_phase phase, bool force_boardenable) { const struct board_match *board = board_match_pci_ids(phase); @@ -2718,20 +2719,21 @@ return 0; } - return board->enable(); + return board->enable(cfg); } -void board_handle_before_superio(bool force_boardenable) +void board_handle_before_superio(struct board_cfg *cfg, bool force_boardenable) { - board_handle_phase(P1, force_boardenable); + board_handle_phase(cfg, P1, force_boardenable); } -void board_handle_before_laptop(bool force_boardenable) +void board_handle_before_laptop(struct board_cfg *cfg, bool force_boardenable) { - board_handle_phase(P2, force_boardenable); + board_handle_phase(cfg, P2, force_boardenable); } -int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, +int board_flash_enable(struct board_cfg *cfg, + const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, bool force_boardenable) { const struct board_match *board = NULL; @@ -2769,7 +2771,7 @@ msg_pinfo("Enabling full flash access for board \"%s %s\"... ", board->vendor_name, board->board_name); - ret = board->enable(); + ret = board->enable(cfg); if (ret) msg_pinfo("FAILED!\n"); else diff --git a/include/programmer.h b/include/programmer.h index ab482e6..047f49a 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -160,6 +160,9 @@ P3 }; +struct board_cfg { +}; + struct board_match { /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; @@ -189,7 +192,7 @@ int max_rom_decode_parallel; const enum test_state status; - int (*enable) (void); /* May be NULL. */ + int (*enable) (struct board_cfg *cfg); /* May be NULL. */ }; extern const struct board_match board_matches[]; @@ -226,9 +229,9 @@ uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); -void board_handle_before_superio(bool force_boardenable); -void board_handle_before_laptop(bool force_boardenable); -int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, bool force_boardenable); +void board_handle_before_superio(struct board_cfg *cfg, bool force_boardenable); +void board_handle_before_laptop(struct board_cfg *cfg, bool force_boardenable); +int board_flash_enable(struct board_cfg *cfg, const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, bool force_boardenable); /* chipset_enable.c */ int chipset_flash_enable(const struct programmer_cfg *cfg); @@ -392,7 +395,7 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev); /* wbsio_spi.c */ -int wbsio_check_for_spi(void); +int wbsio_check_for_spi(struct board_cfg *); #endif /* opaque.c */ diff --git a/internal.c b/internal.c index 5d836e5..c8d0a93 100644 --- a/internal.c +++ b/internal.c @@ -149,6 +149,7 @@ const char *cb_model = NULL; #endif bool force_boardenable = false; + struct board_cfg bcfg; ret = get_params(cfg, &force_boardenable, &force_boardmismatch, @@ -208,7 +209,7 @@ dmi_init(&g_is_laptop); /* In case Super I/O probing would cause pretty explosions. */ - board_handle_before_superio(force_boardenable); + board_handle_before_superio(&bcfg, force_boardenable); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); @@ -221,7 +222,7 @@ #endif /* Check laptop whitelist. */ - board_handle_before_laptop(force_boardenable); + board_handle_before_laptop(&bcfg, force_boardenable); /* * Disable all internal buses by default if we are not sure @@ -247,7 +248,8 @@ * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(cfg); - if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, force_boardenable)) { + if (board_flash_enable(&bcfg, + board_vendor, board_model, cb_vendor, cb_model, force_boardenable)) { msg_perr("Aborting to be safe.\n"); ret = 1; goto internal_init_exit; diff --git a/wbsio_spi.c b/wbsio_spi.c index febe6ed..9f33b18 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -194,7 +194,7 @@ .shutdown = wbsio_spi_shutdown, }; -int wbsio_check_for_spi(void) +int wbsio_check_for_spi(struct board_cfg *cfg) { uint16_t wbsio_spibase = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/71623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7058a693e714a6966a842ae97cc8da7296e63e5e Gerrit-Change-Number: 71623 Gerrit-PatchSet: 6 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: [WIP] Emulate multithreading env for unit tests on OpenBSD
by Anastasia Klimchuk (Code Review) April 1, 2023

April 1, 2023

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/74157 ) Change subject: [WIP] Emulate multithreading env for unit tests on OpenBSD ...................................................................... [WIP] Emulate multithreading env for unit tests on OpenBSD This patch produces lots of compile errors in pthread.h Change-Id: I3d65c125183e60037ad07b9d54b8fffdece5a4e8 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M tests/meson.build M tests/tests.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/74157/1 diff --git a/tests/meson.build b/tests/meson.build index df866d7..d8880f8 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -111,6 +111,7 @@ '-Wl,--wrap=libusb_handle_events_timeout', '-Wl,--wrap=libusb_exit', '-Wl,--gc-sections', + '-lpthread', ] flashrom_tests = executable('flashrom_unit_tests', @@ -120,6 +121,7 @@ '-ffunction-sections', '-fdata-sections', '-U_FORTIFY_SOURCE', + '-Dpthread', ], export_dynamic : true, link_args : mocks + link_args, diff --git a/tests/tests.c b/tests/tests.c index d296a98..240ad21 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -20,8 +20,11 @@ #include "io_real.h" #include <stdio.h> +#include <stdlib.h> #include <string.h> #include <stdint.h> +#include <sys/types.h> +#include <pthread.h> void *not_null(void) { @@ -385,6 +388,13 @@ return 0; } +#if defined(__OpenBSD__) +static void *doing_nothing(void *vargp) { + printf("I am busy multithreading\n"); + return NULL; +} +#endif + int main(int argc, char *argv[]) { int ret = 0; @@ -405,6 +415,15 @@ cmocka_set_message_output(CM_OUTPUT_STDOUT); +#if defined(__OpenBSD__) + /* + * Creating new thread which is doing nothing, to trigger __isthreaded being 1. + * This is a workaround for OpenBSD. + */ + pthread_t thread_id; + pthread_create(&thread_id, NULL, doing_nothing, NULL); +#endif + const struct CMUnitTest helpers_tests[] = { cmocka_unit_test(address_to_bits_test_success), cmocka_unit_test(bitcount_test_success), -- To view, visit https://review.coreboot.org/c/flashrom/+/74157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d65c125183e60037ad07b9d54b8fffdece5a4e8 Gerrit-Change-Number: 74157 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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