January 2023 - flashrom-gerrit

[M] Change in flashrom[master]: tests/chip: Add non-aligned write within a region unit-test
by Edward O'Callaghan (Code Review) 17 Jan '23

17 Jan '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/71659 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: tests/chip: Add non-aligned write within a region unit-test ...................................................................... tests/chip: Add non-aligned write within a region unit-test A written region that is sized below that of the erasure granularity can result in a incorrectly read region that does not include prior content within the region before the write op. This was dealt with in ChromeOS downstream by expanding out the read to match the erase granularity however does not seem to impact upstream. Add a unit-test to avoid regression as this is important behaviour to cover. Change-Id: Id3ce5cd1936f0f348d34a6c77cee15e27a5c353f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71659 Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Evan Benn <evanbenn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M tests/chip.c M tests/tests.c M tests/tests.h 3 files changed, 114 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Evan Benn: Looks good to me, but someone else must approve diff --git a/tests/chip.c b/tests/chip.c index 580f4ea..e82719e 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -418,6 +418,97 @@ free(newcontents); } +void write_nonaligned_region_with_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + static struct io_mock_fallback_open_state data = { + .noc = 0, + .paths = { NULL }, + }; + const struct io_mock chip_io = { + .fallback_open_state = &data, + }; + + struct flashrom_flashctx flashctx = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + const uint32_t mock_chip_size = mock_chip.total_size * KiB; + /* + * Dummyflasher is capable to emulate W25Q128.V, so we ask it to do this. + * Nothing to mock, dummy is taking care of this already. + */ + char *param_dup = strdup("bus=spi,emulate=W25Q128FV"); + + /* FIXME: MOCK_CHIP_CONTENT is buggy within setup_chip, it should also + * not be either 0x00 or 0xFF as those are specific values related to + * either a erased chip or zero'ed heap thus ambigous. + */ +#define MOCK_CHIP_SUBREGION_CONTENTS 0xCC + /** + * Step 0 - Prepare newcontents as contiguous sample data bytes as follows: + * {MOCK_CHIP_SUBREGION_CONTENTS, [..]}. + */ + uint8_t *newcontents = calloc(1, mock_chip_size); + assert_non_null(newcontents); + memset(newcontents, MOCK_CHIP_SUBREGION_CONTENTS, mock_chip_size); + + setup_chip(&flashctx, &layout, &mock_chip, param_dup, &chip_io); + /* Expect to verify only the non-aligned write operation within the region. */ + flashrom_flag_set(&flashctx, FLASHROM_FLAG_VERIFY_AFTER_WRITE, true); + flashrom_flag_set(&flashctx, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, false); + + /** + * Prepare mock chip content and release setup_chip() layout for our + * custom ones. + */ + assert_int_equal(0, flashrom_image_write(&flashctx, newcontents, mock_chip_size, NULL)); + flashrom_layout_release(layout); + + /** + * Create region smaller than erase granularity of chip. + */ + printf("Creating custom region layout... "); + assert_int_equal(0, flashrom_layout_new(&layout)); + printf("Adding and including region0... "); + assert_int_equal(0, flashrom_layout_add_region(layout, 0, (1 * KiB), "region0")); + assert_int_equal(0, flashrom_layout_include_region(layout, "region0")); + flashrom_layout_set(&flashctx, layout); + printf("Subregion layout configuration done.\n"); + + /** + * Step 1 - Modify newcontents as non-contiguous sample data bytes as follows: + * 0xAA 0xAA {MOCK_CHIP_SUBREGION_CONTENTS}, [..]}. + */ + printf("Subregion chip write op..\n"); + memset(newcontents, 0xAA, 2); + assert_int_equal(0, flashrom_image_write(&flashctx, newcontents, mock_chip_size, NULL)); + printf("Subregion chip write op done.\n"); + + /** + * FIXME: A 'NULL' layout should indicate a default layout however this + * causes a crash for a unknown reason. For now prepare a new default + * layout of the entire chip. flashrom_layout_set(&flashctx, NULL); // use default layout. + */ + flashrom_layout_release(layout); + assert_int_equal(0, flashrom_layout_new(&layout)); + assert_int_equal(0, flashrom_layout_add_region(layout, 0, mock_chip_size - 1, "entire")); + assert_int_equal(0, flashrom_layout_include_region(layout, "entire")); + flashrom_layout_set(&flashctx, layout); + + /** + * Expect a verification pass that the previous content within the region, however + * outside the region write length, is untouched. + */ + printf("Entire chip verify op..\n"); + assert_int_equal(0, flashrom_image_verify(&flashctx, newcontents, mock_chip_size)); + printf("Entire chip verify op done.\n"); + + teardown(&layout); + free(param_dup); + free(newcontents); +} + static size_t verify_chip_fread(void *state, void *buf, size_t size, size_t len, FILE *fp) { /* diff --git a/tests/tests.c b/tests/tests.c index a1dcaca..0912f35 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -480,6 +480,7 @@ cmocka_unit_test(read_chip_with_dummyflasher_test_success), cmocka_unit_test(write_chip_test_success), cmocka_unit_test(write_chip_with_dummyflasher_test_success), + cmocka_unit_test(write_nonaligned_region_with_dummyflasher_test_success), cmocka_unit_test(verify_chip_test_success), cmocka_unit_test(verify_chip_with_dummyflasher_test_success), }; diff --git a/tests/tests.h b/tests/tests.h index 6a12fdb..bdcfdae 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -80,6 +80,7 @@ void read_chip_with_dummyflasher_test_success(void **state); void write_chip_test_success(void **state); void write_chip_with_dummyflasher_test_success(void **state); +void write_nonaligned_region_with_dummyflasher_test_success(void **state); void verify_chip_test_success(void **state); void verify_chip_with_dummyflasher_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/71659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id3ce5cd1936f0f348d34a6c77cee15e27a5c353f Gerrit-Change-Number: 71659 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: test_build.sh: Add build_rust
by Evan Benn (Code Review) 17 Jan '23

17 Jan '23

Attention is currently required from: Felix Singer, Patrick Georgi, Evan Benn. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69770 to look at the new patch set (#4). Change subject: test_build.sh: Add build_rust ...................................................................... test_build.sh: Add build_rust Add a function to check the rust projects. cargo test, fmt, and clippy are run to check unit tests, code format, and lint. The rust packages are built against the just compiled 'all' variant of libflashrom. cargo is run offline so that jenkins works. The tests are only run if cargo is installed. BUG=b:242935799 BRANCH=None TEST=./test_build.sh Change-Id: I728f5b856a9161b87b96207f4c3965e7493c33d1 Signed-off-by: Evan Benn <evanbenn(a)chromium.org> --- M test_build.sh 1 file changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/69770/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/69770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I728f5b856a9161b87b96207f4c3965e7493c33d1 Gerrit-Change-Number: 69770 Gerrit-PatchSet: 4 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Evan Benn <evanbenn(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: test_build.sh: Add build_rust
by Evan Benn (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: Felix Singer, Patrick Georgi. Hello Felix Singer, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69770 to look at the new patch set (#3). Change subject: test_build.sh: Add build_rust ...................................................................... test_build.sh: Add build_rust Add a function to check the rust projects. cargo test, fmt, and clippy are run to check unit tests, code format, and lint. The rust packages are built against the just compiled 'all' variant of libflashrom. cargo is run offline so that jenkins works. The tests are only run if cargo is installed. BUG=b:242935799 BRANCH=None TEST=./test_build.sh Change-Id: I728f5b856a9161b87b96207f4c3965e7493c33d1 Signed-off-by: Evan Benn <evanbenn(a)chromium.org> --- M test_build.sh 1 file changed, 49 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/69770/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/69770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I728f5b856a9161b87b96207f4c3965e7493c33d1 Gerrit-Change-Number: 69770 Gerrit-PatchSet: 3 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[master]: Add AMD Ryzen Support & VIA VL805 Support
by ChrisEric1 CECL (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: ChrisEric1 CECL, Thomas Heijligen, Arthur Heymans. Hello build bot (Jenkins), Thomas Heijligen, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72020 to look at the new patch set (#5). Change subject: Add AMD Ryzen Support & VIA VL805 Support ...................................................................... Add AMD Ryzen Support & VIA VL805 Support Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but can downgrade if newer FW is installed using afuwinx64 (vendor tool) This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also came with a AMD Ryzen 3 2200G. Also VL805 is working 100% for RPi4 USB XHCI FW Flashing, I had to change the RPi's chip (W25X10) to use rdid4 instead, since it wouldn't work otherwise. Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M chipset_enable.c M flashrom.8.tmpl M include/programmer.h M programmer_table.c M sb600spi.c M spi25.c A vl805.c 8 files changed, 253 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/72020/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/72020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Gerrit-Change-Number: 72020 Gerrit-PatchSet: 5 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: Add AMD Ryzen Support & VIA VL805 Support
by ChrisEric1 CECL (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: ChrisEric1 CECL, Thomas Heijligen, Arthur Heymans. Hello build bot (Jenkins), Thomas Heijligen, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72020 to look at the new patch set (#4). Change subject: Add AMD Ryzen Support & VIA VL805 Support ...................................................................... Add AMD Ryzen Support & VIA VL805 Support Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but can downgrade if newer FW is installed using afuwinx64 (vendor tool) This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also came with a AMD Ryzen 3 2200G. Also VL805 is working 100% for RPi4 USB XHCI FW Flashing, I had to change the RPi's chip (W25X10) to use rdid4 instead since it wouldn't work otherwise. Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M chipset_enable.c M flashrom.8.tmpl M include/programmer.h M programmer_table.c M sb600spi.c M spi25.c A vl805.c 8 files changed, 239 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/72020/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/72020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Gerrit-Change-Number: 72020 Gerrit-PatchSet: 4 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XL] Change in flashrom[master]: Add AMD Ryzen Support & VIA VL805 Support
by ChrisEric1 CECL (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: ChrisEric1 CECL, Thomas Heijligen, Arthur Heymans. Hello build bot (Jenkins), Thomas Heijligen, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72020 to look at the new patch set (#3). Change subject: Add AMD Ryzen Support & VIA VL805 Support ...................................................................... Add AMD Ryzen Support & VIA VL805 Support Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but can downgrade if newer FW is installed using afuwinx64 (vendor tool) This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also came with a AMD Ryzen 3 2200G. Also VL805 is working 100% for RPi4 USB XHCI FW Flashing, I had to change the RPi's chip (W25X10) to use rdid4 instead since it wouldn't work otherwise. Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M chipset_enable.c A flashchips.h M flashrom.8.tmpl M include/flashchips.h M include/programmer.h M programmer_table.c M sb600spi.c M spi25.c A vl805.c 10 files changed, 1,277 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/72020/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/72020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Gerrit-Change-Number: 72020 Gerrit-PatchSet: 3 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XL] Change in flashrom[master]: Add AMD Ryzen Support & VIA VL805 Support
by ChrisEric1 CECL (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: ChrisEric1 CECL, Thomas Heijligen, Arthur Heymans. Hello build bot (Jenkins), Thomas Heijligen, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72020 to look at the new patch set (#2). Change subject: Add AMD Ryzen Support & VIA VL805 Support ...................................................................... Add AMD Ryzen Support & VIA VL805 Support Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but can downgrade if newer FW is installed using afuwinx64 (vendor tool) This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also came with a AMD Ryzen 3 2200G. Also VL805 is working 100% for RPi4 USB XHCI FW Flashing, I had to change the RPi's chip (W25X10) to use rdid4 instead since it wouldn't work otherwise. Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M chipset_enable.c A flashchips.h M flashrom.8.tmpl M include/flashchips.h M include/programmer.h M programmer_table.c M sb600spi.c M spi25.c A vl805.c 10 files changed, 1,280 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/72020/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Gerrit-Change-Number: 72020 Gerrit-PatchSet: 2 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[master]: Add AMD Ryzen Support & VIA VL805 Support
by ChrisEric1 CECL (Code Review) 16 Jan '23

16 Jan '23

ChrisEric1 CECL has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72020 ) Change subject: Add AMD Ryzen Support & VIA VL805 Support ...................................................................... Add AMD Ryzen Support & VIA VL805 Support Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but can downgrade if newer FW is installed using afuwinx64 (vendor tool) This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also came with a AMD Ryzen 3 2200G. Also VL805 is working 100% for RPi4 USB XHCI FW Flashing, I had to change the RPi's chip (W25X10) to use rdid4 instead since it wouldn't work otherwise. Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M chipset_enable.c M flashchips.c M flashrom.8.tmpl M include/flashchips.h M include/programmer.h M programmer_table.c M sb600spi.c M spi25.c A vl805.c 10 files changed, 330 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/72020/1 diff --git a/Makefile b/Makefile index 425b58c..3148cf8 100644 --- a/Makefile +++ b/Makefile @@ -152,6 +152,7 @@ CONFIG_OGP_SPI \ CONFIG_SATAMV \ CONFIG_SATASII \ + CONFIG_VL805 \ DEPENDS_ON_LIBUSB1 := \ CONFIG_CH341A_SPI \ @@ -516,6 +517,9 @@ # Winchiphead CH341A CONFIG_CH341A_SPI ?= yes +# Enable VIA VL805 programmer for now. +CONFIG_VL805 ?= yes + # Digilent Development board JTAG CONFIG_DIGILENT_SPI ?= yes @@ -767,6 +771,11 @@ PROGRAMMER_OBJS += ch341a_spi.o endif +ifeq ($(CONFIG_VL805), yes) +FEATURE_FLAGS += -D'CONFIG_VL805=1' +PROGRAMMER_OBJS += vl805.o +endif + ifeq ($(CONFIG_DIGILENT_SPI), yes) FEATURE_FLAGS += -D'CONFIG_DIGILENT_SPI=1' PROGRAMMER_OBJS += digilent_spi.o diff --git a/chipset_enable.c b/chipset_enable.c index b9144d1..af6bab2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1772,7 +1772,7 @@ {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, + {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4/FP5/AM4", enable_flash_sb600}, {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, @@ -2179,6 +2179,7 @@ {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, + {0x8086, 0xa3c8, B_S, OK, "Intel", "Comet Lake B460 LPC/eSPI", enable_flash_pch400}, #endif {0}, }; diff --git a/flashchips.c b/flashchips.c index 625fe62..caa82be 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6384,6 +6384,45 @@ { .vendor = "GigaDevice", + .name = "GD25LQ256", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ256, + .total_size = 32768, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1695, 2000}, + }, + + { + .vendor = "GigaDevice", .name = "GD25B128B/GD25Q128B", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, @@ -17893,6 +17932,53 @@ { .vendor = "Winbond", + .name = "W25Q256JW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256JW, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q256FV", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0eabee5..c1436fc 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -417,6 +417,8 @@ .sp .BR "* ch341a_spi" " (for SPI flash ROMs attached to WCH CH341A)" .sp +.BR "* vl805" " (for SPI flash ROMs attached to the VIA VL805 PCIe USB 3.0 Host controller)" +.sp .BR "* digilent_spi" " (for SPI flash ROMs attached to iCEblink40 development boards)" .sp .BR "* jlink_spi" " (for SPI flash ROMs attached to SEGGER J-Link and compatible devices)" @@ -1365,6 +1367,10 @@ .BR "ch341a_spi " programmer The WCH CH341A programmer does not support any parameters currently. SPI frequency is fixed at 2 MHz, and CS0 is used as per the device. +.BR "vl805 " programmer +This module supports SPI flash programming through the VL805/VL806 PCIe-USB 3.0 +Host controller. +.SS .SS .BR "ni845x_spi " programmer .IP @@ -1696,6 +1702,9 @@ .B ogp needs PCI configuration space read access and raw memory access. .sp +.B vl805 +needs PCI configuration space read access and raw memory access. +.sp .BR realtek_mst_i2c_spi " and " parade_lspcon need userspace access to the selected I2C bus. .sp diff --git a/include/flashchips.h b/include/flashchips.h index 5df42dc..c5f7f37 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -400,6 +400,7 @@ #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128CD 0x6018 +#define GIGADEVICE_GD25LQ256 0x6019 #define GIGADEVICE_GD25WQ80E 0x6514 #define GIGADEVICE_GD29GL064CAB 0x7E0601 @@ -977,6 +978,7 @@ #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ +#define WINBOND_NEX_W25Q256JW 0x6019 /* W25Q256JW */ #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ #define WINBOND_NEX_W25Q64JV 0x7017 /* W25Q64JV */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ diff --git a/include/programmer.h b/include/programmer.h index 9e706d5..eae7899 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -25,6 +25,8 @@ #include "flash.h" /* for chipaddr and flashctx */ +extern uint8_t RZN32BM; + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, @@ -60,6 +62,7 @@ extern const struct programmer_entry programmer_atavia; extern const struct programmer_entry programmer_buspirate_spi; extern const struct programmer_entry programmer_ch341a_spi; +extern const struct programmer_entry programmer_vl805; extern const struct programmer_entry programmer_dediprog; extern const struct programmer_entry programmer_developerbox; extern const struct programmer_entry programmer_digilent_spi; diff --git a/programmer_table.c b/programmer_table.c index d58a155..4fb705a 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -152,6 +152,10 @@ &programmer_ch341a_spi, #endif +#if CONFIG_VL805 == 1 + &programmer_vl805, +#endif + #if CONFIG_DIGILENT_SPI == 1 &programmer_digilent_spi, #endif diff --git a/sb600spi.c b/sb600spi.c index 5b9ac45..4c287b7 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -53,6 +53,7 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 +uint8_t RZN32BM = 0; #define SPI100_CMD_CODE_REG 0x45 #define SPI100_CMD_TRIGGER_REG 0x47 @@ -124,6 +125,11 @@ if (rev == 0x4a) { msg_pdbg("Yangtze detected.\n"); return CHIPSET_YANGTZE; + } else if (rev == 0x51 || rev == 0x59 || rev == 0x61) { + //RZN32BM = mmio_readb(sb600_spibar + 0x50) & 0x1; + //amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Ryzen detected.\n"); + return CHIPSET_YANGTZE; /** * FCH chipsets called 'Promontory' are one's with the * so-called SPI100 ip core that uses memory mapping and @@ -513,7 +519,14 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp]); if (spispeed_idx < 0) { - spispeed_idx = 3; /* Default to 16.5 MHz */ + if (amd_gen >= CHIPSET_YANGTZE) + { + spispeed_idx = 1; /* Default to 33.3 MHz */ + } + else + { + spispeed_idx = 3; /* Default to 16.5 MHz */ + } } } if (spispeed_idx < 0) { diff --git a/spi25.c b/spi25.c index f54e4c8..25b5bcb 100644 --- a/spi25.c +++ b/spi25.c @@ -393,7 +393,10 @@ const bool native_4ba, const unsigned int addr) { if (native_4ba || flash->in_4ba_mode) { - if (!spi_master_4ba(flash)) { + if (!spi_master_4ba(flash) && RZN32BM != 1) { + msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n"); + return -1; + } else if (!spi_master_4ba(flash)) { msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n"); return -1; } diff --git a/vl805.c b/vl805.c new file mode 100644 index 0000000..be1093a --- /dev/null +++ b/vl805.c @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019, 2020 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the VIA VL805 programmer hardware by VIA. + * See http://www.via.com/ for more info. + */ + +#include "programmer.h" +#include "spi.h" +#include "flash.h" +//#include "hwaccess.h" +#include "hwaccess_x86_io.h" +#include "platform/pci.h" + +extern const struct dev_entry devs_vl805[]; + +const struct dev_entry devs_vl805[] = { + {0x1106, 0x3483, OK, "VIA", "VL805"}, + {0}, +}; + +static struct pci_dev *dev = NULL; + +static void vl805_setregval(int reg, uint32_t val) +{ + pci_write_long(dev, 0x78, reg); + pci_write_long(dev, 0x7c, val); +} + +static uint32_t vl805_getregval(int reg) +{ + pci_write_long(dev, 0x78, reg); + + return pci_read_long(dev, 0x7c); +} + +/* Some of the registers have unknown purpose and are just used inside the init sequence replay. */ +#define VL805_REG_0x30004 0x00030004 +#define VL805_REG_STOP_POLLING 0x0004000c +#define VL805_REG_WB_EN 0x00040020 +#define VL805_REG_SPI_OUTDATA 0x000400d0 +#define VL805_REG_SPI_INDATA 0x000400e0 +#define VL805_REG_SPI_TRANSACTION 0x000400f0 +#define VL805_REG_CLK_DIV 0x000400f8 +#define VL805_REG_SPI_CHIP_ENABLE_LEVEL 0x000400fc + +/* Send a SPI command to the flash chip. */ +static int vl805_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned int i, j; + uint32_t outdata; + uint32_t indata = 0; + unsigned int curwritecnt = 0; + unsigned int curreadcnt = 0; + + vl805_setregval(VL805_REG_SPI_CHIP_ENABLE_LEVEL, 0x00000000); + + for (j = 0; j < writecnt; j += 4) { + curwritecnt = min(4, writecnt - j); + outdata = 0; + for (i = 0; i < curwritecnt; i++) { + outdata <<= 8; + outdata |= writearr[j + i]; + } + vl805_setregval(VL805_REG_SPI_OUTDATA, outdata); + vl805_setregval(VL805_REG_SPI_TRANSACTION, 0x00000580 | (curwritecnt << 3)); + } + + /* Superfluous, the original driver doesn't do that, but we want to have a quiet bus during read. */ + vl805_setregval(VL805_REG_SPI_OUTDATA, 0); + + for (j = 0; j < readcnt; j += 4) { + curreadcnt = min(4, readcnt - j); + vl805_setregval(VL805_REG_SPI_TRANSACTION, 0x00000580 | (curreadcnt << 3)); + indata = vl805_getregval(VL805_REG_SPI_INDATA); + for (i = 0; i < curreadcnt; i++) { + unsigned pos = curreadcnt - (i + 1); + readarr[j + i] = (indata >> (8 * pos)) & 0xff; + } + } + + vl805_setregval(VL805_REG_SPI_CHIP_ENABLE_LEVEL, 0x00000001); + + return 0; +} + +static const struct spi_master spi_master_vl805 = { + .max_data_read = 64 * 1024, /* Maximum data read size in one go (excluding opcode+address). */ + .max_data_write = 256, /* Maximum data write size in one go (excluding opcode+address). */ + .command = vl805_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, + .probe_opcode = default_spi_probe_opcode, +}; + +static void vl805_programmer_active(uint8_t val) +{ + pci_write_byte(dev, 0x43, val); +} + +static int vl805_shutdown(void *data) +{ + /* Shutdown stuff. */ + vl805_programmer_active(0x0); + + return 0; +} + +int vl805_init(void); + +int vl805_init(void) +{ + uint32_t val; + + #if defined(__i386__) || defined(__x86_64__) + if (rget_io_perms()) + return 1; + #endif + + dev = pcidev_init(devs_vl805, PCI_BASE_ADDRESS_0); /* Actually no BAR setup needed at all. */ + if (!dev) + return 1; + + vl805_programmer_active(0x1); + val = pci_read_long(dev, 0x50); + msg_pdbg("VL805 firmware version 0x%08x\n", val); + vl805_programmer_active(0x0); + + /* Some sort of init sequence, just copied from the logs. */ + vl805_programmer_active(0x1); + + vl805_setregval(VL805_REG_SPI_CHIP_ENABLE_LEVEL, 0x00000001); + vl805_setregval(VL805_REG_0x30004, 0x00000200); + vl805_setregval(VL805_REG_WB_EN, 0xffffff01); + vl805_setregval(VL805_REG_STOP_POLLING, 0x00000001); + + /* We send 4 uninitialized(?) bytes to the flash chip here. */ + vl805_setregval(VL805_REG_SPI_TRANSACTION, 0x000005a0); + vl805_setregval(VL805_REG_CLK_DIV, 0x0000000a); + + /* Some sort of cleanup sequence, just copied from the logs. */ + vl805_setregval(VL805_REG_SPI_TRANSACTION, 0x00000000); + vl805_programmer_active(0x0); + + register_shutdown(vl805_shutdown, NULL); + vl805_programmer_active(0x1); + + register_spi_master(&spi_master_vl805, NULL); + + return 0; +} + +const struct programmer_entry programmer_vl805 = { + .name = "vl805", + .type = PCI, + .devs.dev = devs_vl805, + .init = vl805_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, +}; -- To view, visit https://review.coreboot.org/c/flashrom/+/72020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7452b169ad89e0a884a46acc6a0499e97bb6ff7e Gerrit-Change-Number: 72020 Gerrit-PatchSet: 1 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashrom.c: Add new erase_by_layout and walk_bylayout implementations
by Aarya (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan. Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71173 ) Change subject: flashrom.c: Add new erase_by_layout and walk_bylayout implementations ...................................................................... Patch Set 14: (2 comments) File flashrom.c: https://review.coreboot.org/c/flashrom/+/71173/comment/98be0342_dd628089 PS6, Line 1695: //not enough memory : if (!curcontents || !newcontents) { : ret = 1; : goto _ret; : } > delete? Done https://review.coreboot.org/c/flashrom/+/71173/comment/bcf7a74b_a699f252 PS6, Line 1701: (uint8_t*) > don't cast, just use the correct type in the first place in the function definition. The newcontents buffer may b written while aligning boundaries. So the newcontents needs to be casted as it is `const void *` -- To view, visit https://review.coreboot.org/c/flashrom/+/71173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Gerrit-Change-Number: 71173 Gerrit-PatchSet: 14 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Jan 2023 18:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashrom.c: Add new erase_by_layout and walk_bylayout implementations
by Aarya (Code Review) 16 Jan '23

16 Jan '23

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan. Hello build bot (Jenkins), Simon Buhrow, Thomas Heijligen, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/71173 to look at the new patch set (#14). Change subject: flashrom.c: Add new erase_by_layout and walk_bylayout implementations ...................................................................... flashrom.c: Add new erase_by_layout and walk_bylayout implementations Add [erase,walk]_by_layout_new to use optimised implementations of the erase function selection algorithm. Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M flashrom.c 1 file changed, 88 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/71173/14 -- To view, visit https://review.coreboot.org/c/flashrom/+/71173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Gerrit-Change-Number: 71173 Gerrit-PatchSet: 14 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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