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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/eb9c9ef3_248e7cbf
PS1, Line 7: flashrom
> nit: ichspi. […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/879dad7a_9920fea0
PS1, Line 1390: REGREAD32
> Isn't this register 16-bit?
Hardware Sequencing Flash Status and Control
(BIOS_HSFSTS_CTL)—Offset 4h, 32 bit register
https://review.coreboot.org/c/flashrom/+/61854/comment/f5696c66_c8f57313
PS1, Line 1392: } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
> This loop could potentially never exit.
It depends on HW operation and here is what EDS says, so, I believe we might not run into such issue. Also, *Software must only program the next command when this bit is 0.*
SPI Cycle In Progress (H_SCIP): Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register.
This bit remains set until the cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can determine when read data
is valid and/or when it is safe to begin programming the next command.
Software must only program the next command when this bit is 0.
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Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#2).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI
transaction is complete before initiating newer command.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: flashrom: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
flashrom: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI
transaction is complete before initiating newer command.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/1
diff --git a/ichspi.c b/ichspi.c
index 117ff8d..ac4e3eb 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1366,6 +1366,35 @@
return 1;
}
+/*
+ * As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
+ * sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
+ * Control register.
+ *
+ * This bit remains set until the cycle completes on the SPI interface.
+ * Hardware automatically sets and clears this bit so that software can
+ * determine when read data is valid and/or when it is safe to begin
+ * programming the next command.
+ *
+ * Software must initiate the next SPI transaction when this bit is 0.
+ *
+ * Added blocking mechanism without timeout to ensure previous SPI transaction
+ * is complete before initiating newer command.
+ */
+static void ich_wait_for_hwseq_spi_cycle_complete(void)
+{
+ uint32_t hsfsts;
+
+ msg_pspew("SPI Transaction in progress ");
+ do {
+ hsfsts = REGREAD32(ICH9_REG_HSFS);
+ msg_pspew("..");
+ } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
+
+ msg_pspew("\nSPI Transaction done!\n");
+ return;
+}
+
static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
unsigned int len)
{
@@ -1396,6 +1425,9 @@
return -1;
}
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
ich_hwseq_set_addr(addr);
@@ -1438,6 +1470,9 @@
/* as well as flash chip page borders as demanded in the Intel datasheets. */
block_len = min(block_len, 256 - (addr & 0xFF));
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
ich_hwseq_set_addr(addr);
hsfc = REGREAD16(ICH9_REG_HSFC);
hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
@@ -1474,6 +1509,9 @@
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
while (len > 0) {
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
ich_hwseq_set_addr(addr);
/* Obey programmer limit... */
block_len = min(len, flash->mst->opaque.max_data_write);
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61578 )
Change subject: internal.c: Seperate out get_params() from internal_init()
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61578/comment/6960221d_75d2aa88
PS2, Line 13: TEST=`make`
> Does this need anymore testing? like `flashrom -p internal` for example?
Tested on dooly / Comet Lake DUT.
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Nikolai Artemiev has uploaded a new patch set (#3) to the change originally created by Edward O'Callaghan. ( https://review.coreboot.org/c/flashrom/+/61578 )
Change subject: internal.c: Seperate out get_params() from internal_init()
......................................................................
internal.c: Seperate out get_params() from internal_init()
Move all programmer parameter wrangling into its own
function.
BUG=none
TEST=`flashrom -p internal` on dooly DUT.
Change-Id: I66bb370eb0466c5c838621762a6ba825c44567d4
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---
M internal.c
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git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/61578/3
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#34).
Change subject: libflashrom,writeprotect: add functions for reading/writing WP configs
......................................................................
libflashrom,writeprotect: add functions for reading/writing WP configs
New functions are exposed through the libflashrom API for
reading/writing chip WP configuartion: `flashrom_wp_{read,write}_cfg()`.
The input/output of these functions is a an opaque `struct
flashrom_wp_cfg` instance, which includes the flash protection range and
status register protection mode.
This commit also adds `{read,write}_wp_bits()` helper functions that
read/write chip-specific WP configuration bits.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.c
M libflashrom.h
M writeprotect.c
M writeprotect.h
4 files changed, 358 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/34
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