Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan.
Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67717 )
Change subject: spi.c: Add AT45 & SF25F erasefn opcode mapping
......................................................................
Patch Set 7:
(2 comments)
File spi.c:
https://review.coreboot.org/c/flashrom/+/67717/comment/ebfda456_06a359b4
PS6, Line 229: 0x00
> `NULL`
Done
https://review.coreboot.org/c/flashrom/+/67717/comment/a4dcdd84_a0effb34
PS6, Line 229: Assuming 0x00
> ..
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70306
to look at the new patch set (#3).
Change subject: spi.c: Make first parameter of spi_master.probe_opcode() const
......................................................................
spi.c: Make first parameter of spi_master.probe_opcode() const
Make (struct flashctx *) -> (const struct flashctx *) in spi_master.probe_opcode functions.
Change-Id: Ied840dbbcbe50e44cabd32eea37b7257b5e9c957
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M dummyflasher.c
M ichspi.c
M include/programmer.h
M spi.c
4 files changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/70306/3
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Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70306 )
Change subject: spi.c: Make first parameter of spi_master.probe_opcode() const
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70306/comment/5939aa83_87632c3e
PS1, Line 7: spi.c: Make parameter (struct flashctx *) const
> tree: Make first parameter of spi_master. […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70306
to look at the new patch set (#2).
Change subject: spi.c: Make first parameter of spi_master.probe_opcode() const
......................................................................
spi.c: Make first parameter of spi_master.probe_opcode() const
Make (struct flashctx *) -> (const struct flashctx *) in spi_master.probe_opcode
functions.
Change-Id: Ied840dbbcbe50e44cabd32eea37b7257b5e9c957
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M dummyflasher.c
M ichspi.c
M include/programmer.h
M spi.c
4 files changed, 18 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/70306/2
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Aarya has uploaded a new patch set (#7) to the change originally created by Thomas Heijligen. ( https://review.coreboot.org/c/flashrom/+/67717 )
Change subject: spi.c: Add AT45 & SF25F erasefn opcode mapping
......................................................................
spi.c: Add AT45 & SF25F erasefn opcode mapping
Change-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M include/chipdrivers.h
M spi.c
2 files changed, 57 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/67717/7
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Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66717 )
Change subject: flashrom.c: Update check_block_eraser function to use probe opcode
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS3:
> Insert one before this. Thanks.
Done
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70006 )
Change subject: layout: Check return values for strdup in register_include_arg
......................................................................
Patch Set 4:
(1 comment)
File layout.c:
https://review.coreboot.org/c/flashrom/+/70006/comment/3a610984_322c53ae
PS2, Line 139: || file == NULL
> Oh yes, thanks for spotting memory leak! I missed that, fixed by `goto error`. […]
Yes, it requires setting `name` to NULL in line 122 as well so that it is initialized. Anyway, I don't have objections.
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70306 )
Change subject: spi.c: Make parameter (struct flashctx *) const
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70306/comment/40af8d8e_ee2649fc
PS1, Line 7: spi.c: Make parameter (struct flashctx *) const
tree: Make first parameter of spi_master.probe_opcode() const
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Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev.
Nikolai Artemiev has uploaded a new patch set (#7) to the change originally created by Edward O'Callaghan. ( https://review.coreboot.org/c/flashrom/+/69517 )
Change subject: flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
......................................................................
flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
The full writeprotect implementation has proper support and
ability to unlock flash over spi25_statusreg.c. Therefore if
the required bits are available for the given chip prefer
proper writeprotect support instead of adhoc spi25_statusreg.c
helpers.
BUG=b:237485865
BRANCH=none
TEST=make
Change-Id: I74b3f5d3a17749ea60485b916b2d87467a5d8b2f
CoAuthored-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.c
1 file changed, 69 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/69517/7
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Nikolai Artemiev has uploaded a new patch set (#6) to the change originally created by Edward O'Callaghan. ( https://review.coreboot.org/c/flashrom/+/69517 )
Change subject: flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
......................................................................
flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
The full writeprotect implementation has proper support and
ability to unlock flash over spi25_statusreg.c. Therefore if
the required bits are available for the given chip prefer
proper writeprotect support instead of adhoc spi25_statusreg.c
helpers.
BUG=b:237485865
BRANCH=none
TEST=make
Change-Id: I74b3f5d3a17749ea60485b916b2d87467a5d8b2f
CoAuthored-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.c
M include/flash.h
2 files changed, 70 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/69517/6
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