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Change subject: spi: Make 'default_spi_write_aai' the default unless defined
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Patchset:
PS1:
> Addressed the first part in the commit message by making clear the mathematical constraint here in p […]
I think the patch is fine as it is now. A rename might be good, but I agree that should be done in a separate patch. I remember we didn't do the rename in others.
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Change subject: cli_classic.c: Allow ctrl of behaviour with WO and RO regions
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Patch Set 5: Code-Review+1
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70517 )
Change subject: flashrom: Check for flash access restricitons in erase path
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70517/comment/cefe0a1f_c7f06a52
PS9, Line 7: flashrom: Check for flash access restricitons in erase path
typo: restrictions
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Change subject: flashrom_tester: Drop dediprog, ec, and servo targets
......................................................................
Patch Set 3: Code-Review+2
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qianfan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70529 )
Change subject: Add initial CH347T SPI programmer
......................................................................
Patch Set 3:
(2 comments)
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/f1df6b3a_e10a2e94
PS3, Line 119: SPI_NSS_HARD
> The vendor drivers set this to 0x0200, which is SPI_NSS_SOFT in the enum. […]
OK, I will change it to SPI_NSS_SOFT, as same as the vendor drivers.
https://review.coreboot.org/c/flashrom/+/70529/comment/2e197e3d_ebbf2b7b
PS3, Line 420: 0
> Rewording what I meant: Mode 1 uses interface 2, so the code currently will not correctly detach the […]
Got it. I will make a change.
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Change subject: Add initial CH347T SPI programmer
......................................................................
Patch Set 3:
(3 comments)
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/74e885a0_6b4fd161
PS3, Line 84: enum spi_nss {
: SPI_NSS_SOFT = 0x0200,
: SPI_NSS_HARD = 0x0000
: };
> I don't know what this means, maybe it is used for spi device. […]
stlinkv3_spi.c also uses NSS, and that code labels it as meaning "Negated Slave Select". After reading about hardware vs software NSS for ST Link devices, it seems like it isn't what I thought it was. This is an article that sort of explains it: https://fastbitlab.com/stm32-spi-hardware-software-slave-managements/
In any case, I could never make those bits change using any settings while calling `CH347SPI_Init` in the vendor driver so it likely doesn't really matter for our purposes.
https://review.coreboot.org/c/flashrom/+/70529/comment/6dbec451_3a50e5b3
PS3, Line 119: SPI_NSS_HARD
The vendor drivers set this to 0x0200, which is SPI_NSS_SOFT in the enum. Not that it seems to make any difference in the behavior though
https://review.coreboot.org/c/flashrom/+/70529/comment/63335074_fae88ede
PS3, Line 420: 0
> Mode 1 uses interface 2, and the programmer currently fails if the vendor kernel driver is loaded.
Rewording what I meant: Mode 1 uses interface 2, so the code currently will not correctly detach the vendor kernel driver attached to interface 2 and not 0, causing flashrom to fail as libusb cannot take control of the chip. It would probably be good to move the interface number into ch347_device (mode 2 uses interface 1)
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Change subject: Add initial CH347T SPI programmer
......................................................................
Patch Set 3:
(5 comments)
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/73f4e4a5_38ceb749
PS2, Line 34: CH347_CMD_SPI_CONTROL,
> Maybe make it more clear that this controls the CS lines?
Yes
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/49c7c3b1_ddb65f6b
PS3, Line 30: #define CH347_MAX_DATA_READ 4096
> This probably could be set to a higher value. […]
the 512 and 4096 is as same as WCH's dll so I copied those value there. And I try talk with WCH's FAE to detect the maximum value.
PS: I had test the CH347_MAX_DATA_READ, it also work even it is 1MiB.
https://review.coreboot.org/c/flashrom/+/70529/comment/910e1e3e_bb9d186b
PS3, Line 41: enum spi_prescaler {
: SPI_BAUDRATEPRESCALER_2 = 0x00,
: SPI_BAUDRATEPRESCALER_4 = 0x08,
: SPI_BAUDRATEPRESCALER_8 = 0x10,
: SPI_BAUDRATEPRESCALER_16 = 0x18,
: SPI_BAUDRATEPRESCALER_32 = 0x20,
: SPI_BAUDRATEPRESCALER_64 = 0x28,
: SPI_BAUDRATEPRESCALER_128 = 0x30,
: SPI_BAUDRATEPRESCALER_256 = 0x38
: };
> Alternatively the prescaler values could start from 1 and then the formula would be freq = 60 MHz / […]
CH347 is based on CH32VF3x, SPIx_CTLR1:BR[2:0] control the spi's clock, it has this defines:
000:FPCLK/2
001:FPCLK/4
010:FPCLK/8
011:FPCLK/16
100:FPCLK/32
101:FPCLK/64
110:FPCLK/128
111:FPCLK/256
So "enum spi_prescaler" is started from 1.
https://review.coreboot.org/c/flashrom/+/70529/comment/27df5846_614ff79e
PS3, Line 84: enum spi_nss {
: SPI_NSS_SOFT = 0x0200,
: SPI_NSS_HARD = 0x0000
: };
> I would rename these to be clearer what it does, maybe `enum spi_cs`, `SPI_CS_SOFTWARE`, and `SPI_CS […]
I don't know what this means, maybe it is used for spi device. On spi master, we control cs by command 0xC1.
https://review.coreboot.org/c/flashrom/+/70529/comment/46662d37_9b69bf3f
PS3, Line 179: buf, n + 3,
> This may go over the 512 byte max packet size of the write endpoint since n can be up to 512 due to […]
Let's use the default value as same as DLL. We can update this code when we got a clear reply that it can support a larger value.
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Evan Benn has uploaded a new patch set (#3) to the change originally created by Nikolai Artemiev. ( https://review.coreboot.org/c/flashrom/+/69921 )
Change subject: flashrom_tester: Drop dediprog, ec, and servo targets
......................................................................
flashrom_tester: Drop dediprog, ec, and servo targets
None of these targets have been maintained or used for several years:
dediprog:
- Wasn't accepted by the argument filter in main.rs.
ec:
- Is incompatible with most tests because the EC only supports one
protection range.
servo:
- Has been broken for >3 years because it uses the programmer string
"ft2231_spi:type=servo-v2", where "ft2231" should be "ft2232".
BUG=b:239357853
BRANCH=none
TEST=flashrom_tester on dedede
Change-Id: Iee94f6bb5ff8c5451acb8bcaabf28119006d0ef5
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M util/flashrom_tester/flashrom/src/cmd.rs
M util/flashrom_tester/flashrom/src/lib.rs
M util/flashrom_tester/src/main.rs
M util/flashrom_tester/src/tester.rs
4 files changed, 30 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/69921/3
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70517 )
Change subject: flashrom: Check for flash access restricitons in erase path
......................................................................
Patch Set 9: Code-Review+1
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