March 2017 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 29 Mar '17

29 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18962 to look at the new patch set (#2). Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 221 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/2 -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <dhendrix(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in flashrom[staging]: ich_descriptors: Fix range checks for dumps
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19031 ) Change subject: ich_descriptors: Fix range checks for dumps ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/57/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/73/ : SUCCESS -- To view, visit https://review.coreboot.org/19031 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18973 ) Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/56/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/72/ : SUCCESS -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ich_descriptors: Fix range checks for dumps
by Nico Huber (Code Review) 28 Mar '17

28 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/19031 ) Change subject: ich_descriptors: Fix range checks for dumps ...................................................................... ich_descriptors: Fix range checks for dumps These explicit off-by-one calculations were... off-by-one. Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/19031/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 92318df..4260a8c 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -725,7 +725,7 @@ } /* map */ - if (len < (4 + pch_bug_offset) * 4 - 1) + if (len < (4 + pch_bug_offset) * 4) return ICH_RET_OOB; desc->content.FLVALSIG = dump[0 + pch_bug_offset]; desc->content.FLMAP0 = dump[1 + pch_bug_offset]; @@ -733,14 +733,14 @@ desc->content.FLMAP2 = dump[3 + pch_bug_offset]; /* component */ - if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + if (len < getFCBA(&desc->content) + 3 * 4) return ICH_RET_OOB; desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; /* region */ - if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + if (len < getFRBA(&desc->content) + 5 * 4) return ICH_RET_OOB; desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; @@ -749,7 +749,7 @@ desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; /* master */ - if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + if (len < getFMBA(&desc->content) + 3 * 4) return ICH_RET_OOB; desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; @@ -764,7 +764,7 @@ * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A * check ensures that the maximum offset actually accessed is available. */ - if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + if (len < getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8)) return ICH_RET_OOB; for (i = 0; i < desc->upper.VTL/2; i++) { -- To view, visit https://review.coreboot.org/19031 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 28 Mar '17

28 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18973 to look at the new patch set (#3). Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... WIP: ich_descriptors: Update for Intel Skylake Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 262 insertions(+), 189 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/3 -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18973 ) Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom_gerrit/71/ : FAILURE https://qa.coreboot.org/job/flashrom-customrules/55/ : SUCCESS -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 27 Mar '17

27 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18973 to look at the new patch set (#2). Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... WIP: ich_descriptors: Update for Intel Skylake Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h 2 files changed, 161 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/2 -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 24 Mar '17

24 Mar '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/18962/1/ichspi.c File ichspi.c: PS1, Line 947: /* Program offset in flash into FADDR while preserve the reserved bits : * and clearing the 25. address bit which is only useable in hwseq. */ : temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; : REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); Probably needs an update. -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by build bot (Jenkins) (Code Review) 24 Mar '17

24 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18973 ) Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom_gerrit/70/ : FAILURE https://qa.coreboot.org/job/flashrom-customrules/54/ : SUCCESS -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 24 Mar '17

24 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18973 ) Change subject: WIP: ich_descriptors: Update for Intel Skylake ...................................................................... WIP: ich_descriptors: Update for Intel Skylake Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.h 1 file changed, 95 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/1 diff --git a/ich_descriptors.h b/ich_descriptors.h index df4dd76..ab4af1e 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -77,7 +77,7 @@ NC :2, /* Number Of Components */ :6, FRBA :8, /* Flash Region Base Address */ - NR :3, /* Number Of Regions */ + NR :3, /* Number Of Regions (reserved from Skylake on) */ :5; }; }; @@ -94,9 +94,10 @@ union { /* 0x0c */ uint32_t FLMAP2; struct { - uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ - MSL :8, /* MCH Strap Length */ - :16; + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */ + RIL :8; /* Register Init Length (new since Hawell) */ }; }; }; @@ -116,7 +117,8 @@ * Patsburg: 50 30 5 0:2, 3:5 * Panther Point/7 50 30 5 0:2, 3:5 * Lynx Point/8: 50 30 7 0:3, 4:7 - * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? + * Wildcat Point/9: 50 ?? (multi I/O) 7 ?:?, ?:? + * Sunrise Point/100: 48 ?? 7 0:3, 4:7 */ struct { uint32_t :17, @@ -149,106 +151,107 @@ }; }; union { /* 0x08 */ - uint32_t FLPB; /* Flash Partition Boundary Register */ + uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */ struct { uint32_t FPBA :13, /* Flash Partition Boundary Addr */ :19; }; - }; -}; - -struct ich_desc_region { - union { - uint32_t FLREGs[5]; + uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */ struct { - struct { /* FLREG0 Flash Descriptor */ - uint32_t reg0_base :13, - :3, - reg0_limit :13, - :3; - }; - struct { /* FLREG1 BIOS */ - uint32_t reg1_base :13, - :3, - reg1_limit :13, - :3; - }; - struct { /* FLREG2 ME */ - uint32_t reg2_base :13, - :3, - reg2_limit :13, - :3; - }; - struct { /* FLREG3 GbE */ - uint32_t reg3_base :13, - :3, - reg3_limit :13, - :3; - }; - struct { /* FLREG4 Platform */ - uint32_t reg4_base :13, - :3, - reg4_limit :13, - :3; - }; + uint32_t invalid_instr4 :8, + invalid_instr5 :8, + invalid_instr6 :8, + invalid_instr7 :8; }; }; }; -struct ich_desc_master { - union { - uint32_t FLMSTR1; - struct { - uint32_t BIOS_req_ID :16, - BIOS_descr_r :1, - BIOS_BIOS_r :1, - BIOS_ME_r :1, - BIOS_GbE_r :1, - BIOS_plat_r :1, - :3, - BIOS_descr_w :1, - BIOS_BIOS_w :1, - BIOS_ME_w :1, - BIOS_GbE_w :1, - BIOS_plat_w :1, - :3; +#define MAX_NUM_FLREGS 10 /* 16 on unsupported Lewisburg PCH */ +union ich_desc_region { + uint32_t FLREG[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ + /* + * Number of entries and width differ on various generations: + * + * Chipset/Generation #FLREGs width (bits) + * ICH8 .. Panther Point/7 5 13 + * Lynx Point/8 .. Wildcat Point/9 7 15 + * Sunrise Point/100 .. 10 15 + */ + struct { + uint32_t base :15, + :1, + limit :15, + :1; + } reg[MAX_NUM_FLREGS]; +}; + +union ich_desc_master { + /* For pre-Skylake platforms */ + struct { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; }; }; + /* From Skylake on */ + #define MAX_NUM_MASTERS 5 /* 6 on unsupported Lewisburg PCH */ union { - uint32_t FLMSTR2; + uint32_t FLMSTR[MAX_NUM_MASTERS]; /* Flash Masters */ struct { - uint32_t ME_req_ID :16, - ME_descr_r :1, - ME_BIOS_r :1, - ME_ME_r :1, - ME_GbE_r :1, - ME_plat_r :1, - :3, - ME_descr_w :1, - ME_BIOS_w :1, - ME_ME_w :1, - ME_GbE_w :1, - ME_plat_w :1, - :3; - }; - }; - union { - uint32_t FLMSTR3; - struct { - uint32_t GbE_req_ID :16, - GbE_descr_r :1, - GbE_BIOS_r :1, - GbE_ME_r :1, - GbE_GbE_r :1, - GbE_plat_r :1, - :3, - GbE_descr_w :1, - GbE_BIOS_w :1, - GbE_ME_w :1, - GbE_GbE_w :1, - GbE_plat_w :1, - :3; - }; + uint32_t :8, + read :12, + write :12; + } master[MAX_NUM_MASTERS]; }; }; -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit March 2017