build # flashrom -w coreboot.rom
flashrom v0.9.2-r1001 on Linux 2.6.36-gentoo-r5 (x86_64), built with libpci 3.1.4, GCC 4.4.4 flashrom is free software, get the source code at http://www.flashrom.org
No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF080A" (1024 KB, LPC) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === Note: If the following flash access fails, try -m <vendor>:<mainboard>. Writing flash chip... Erasing flash chip... SUCCESS. Programming page: DONE!ss: 0x000ff000 COMPLETE. Verifying flash... VERIFIED.
After running flashrom -r backup.bin and comparing the checksum to the original image, I found they were identical.
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