build # flashrom -w coreboot.rom<br><br>flashrom v0.9.2-r1001 on Linux 2.6.36-gentoo-r5 (x86_64), built with libpci 3.1.4, GCC 4.4.4<br>flashrom is free software, get the source code at <a href="http://www.flashrom.org">http://www.flashrom.org</a><br>
<br>No coreboot table found.<br>Found chipset &quot;NVIDIA CK804&quot;, enabling flash write... OK.<br>This chipset supports the following protocols: Non-SPI.<br>Calibrating delay loop... OK.<br>Found chip &quot;SST SST49LF080A&quot; (1024 KB, LPC) at physical address 0xfff00000.<br>
===<br>This flash part has status UNTESTED for operations: ERASE WRITE<br>The test status of this chip may have been updated in the latest development<br>version of flashrom. If you are running the latest development version,<br>
please email a report to <a href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> if any of the above operations<br>work correctly for you with this flash part. Please include the flashrom<br>output with the additional -V option for all operations you tested (-V, -Vr,<br>
-Vw, -VE), and mention which mainboard or programmer you tested.<br>Thanks for your help!<br>===<br>Note: If the following flash access fails, try -m &lt;vendor&gt;:&lt;mainboard&gt;.<br>Writing flash chip... Erasing flash chip... SUCCESS.<br>
Programming page: DONE!ss: 0x000ff000<br>COMPLETE.<br>Verifying flash... VERIFIED.<br><br>After running flashrom -r backup.bin and comparing the checksum to the original image, I found they were identical.<br>