flashrom

flashrom@flashrom.org

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9113 discussions

Flashroom Info - Attempt to read ROM from Asus ROG Zenith II Extreme
by ujqpwyztbiswjvwv 25 Jul '24

25 Jul '24

Hi Flashrom Developers, I’m curiious about the BIOS on my motherboard, and am hoping to snoop around to figure out if it’s possible to replace with correboot. My motherboard is a Asus ROG Zenith II Extreme, which has an AMD TRX40 Chipset. I’m guessing I need to use a hardware programmer. Are there any that you reccomend? I’ve looked through https://flashrom.org/supported_hw/supported_prog/index.html and https://github.com/flashrom/flashrom/blob/main/programmer_table.c I have a J-Link right now, so that may be the easiest route for me. I attempted to use flashrom and it failed. Per the instructions, here is the output: flashrom unknown on Linux 6.1.0-21-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x61 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Thanks, Isaac

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flashrom release v1.4.0 is out
by Anastasia Klimchuk 25 Jul '24

25 Jul '24

Good day everyone, flashrom release v1.4.0 is out! Tarball: https://download.flashrom.org/releases/flashrom-1.4.0.tar.xz Signature: https://download.flashrom.org/releases/flashrom-1.4.0.tar.xz.asc Fingerprint: 6E6E F9A0 BA47 8006 E277 6E4C C037 BB41 3134 D111 Checkout from git repository: by the tag v1.4.0 on the main branch. Release notes published: https://flashrom.org/release_notes/v_1_4.html Since the previous v1.3.0 we got 438 commits from 73 authors. Thank you all so much! Many thanks to all our amazing contributors, reviewers, developers, maintainers, and everyone who supports flashrom in any way <3 All the patches that have been ready and waiting, will be submitted very soon. We return back to the normal development process. -- Anastasia.

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FAILED: <Lantis>
by Abhinav Thulung 24 Jul '24

24 Jul '24

Hello flashrom, I was trying to disable WP with you software and decided to type “flashrom —erase” It now says: “Transaction error between offset 0x00bca000 and 0x00bca000 (= 0x00bca000 + 0)! ERASE_FALIED FAILED! Your flash chip is in an unknown state.” It then shows some ways to seek help, the it says: “DO NOT REBOOT OR POWEROFF! FAILED” What should I do? I can’t leave this like that forever. Please respond, I know you guys are busy people, but I would be forever grateful if you help me. Thanks. P.S: I have no ch341a USB or soldering items on me, I have no idea what I’m doing.

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HELPPPP
by Anonymous 23 Jul '24

23 Jul '24

hello people, i want to restore my chromebook to its original state after installing windows. i booted it into a live ubuntu usb and i connected it into the internet, i installed curl and then i ran this command: cd ~; curl -L -O https://coolstar.org/chromebook/setup... && sudo bash setup-firmware.sh it gave me an error cuz they removed the file so i downloaded an archived one using the wayback machine. then i did sudo bash setup-firmware.sh and it gave me this error: Getting device/system info... Unable to read current firmware; cannot continue. Either add 'iomem=relaxed' to your kernel parameters, or trying running from a Live USB with a more permissive kernel (eg, Ubuntu). See https://www.flashrom.org/FAQ for more info

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Could not read internal BIOS/UEFI FW chip on ASRock B450M Pro4 R2.0
by Jacob G 22 Jul '24

22 Jul '24

Hello - I was told to email by flashrom :) I tried to read the BIOS chip in my ASRock B450M Pro4 R2.0, with UEFI firmware version 10.20 (recently released - less than a month old) with flashrom and it failed: [nix-shell:~]$ sudo flashrom -p internal -r asrock-b450mpro4-efifw.rom [sudo] password for jrg: flashrom v1.3.0 on Linux 6.6.39 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x51 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Here is your requested information. The output of lspci -nnvx is in the attached .log file.

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release v1.4.0 plan and timeline
by Anastasia Klimchuk 11 Jul '24

11 Jul '24

Good day everyone, We are preparing to do v1.4.0 release and below is the plan and timeline. TLDR: The release will be from the main branch. Testing and bug fixing window is from 28 June to 26 July, any help is highly appreciated! https://flashrom.org/how_to_support_flashrom.html#building-and-testing Known issue: https://ticket.coreboot.org/issues/370 More details: #1 In two weeks, on 28 June, we update the VERSION file to 1.4.0-rc1 and put a tag v1.4.0-rc1 (which means the first release candidate). From that moment, we open a 4-weeks window for testing and bugfixing. That is from 28 June to 26 July. During this window, bug fixes will be reviewed and submitted, but things like new features/refactorings etc will need to wait until 26 July. Just to be clear, any patch with new feature can be pushed and reviewed, it just won't be submitted until 26 July. Any help is very much appreciated during this time. #2 If needed, we can create v1.4.0-rc2 during the window #3 On 26 July, we update the VERSION file to 1.4.0 and put a tag v1.4.0 Then, there will be an announcement about the release, with the link to full release notes. After all that, VERSION file will be updated to 1.5.0-devel, all the patches that are ready and have been waiting, will be submitted, and everything gets back to normal. If later a point release is needed, it will be branched from v1.4.0 tag. Also, we plan to do another release later this year. So everything that didn't get submitted until 28 June (and by this didn't get into 1.4), can get into 1.5 later this year. Note there is a known issue: https://ticket.coreboot.org/issues/370 -- Anastasia.

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CHIPSET: Intel Kaby Lake U w/ iHDCP2.2 Prem
by Jason Whitaker 09 Jul '24

09 Jul '24

Unsure of board URL, this is an Asus Chromebox for Google Meet: https://www.asus.com/displays-desktops/mini-pcs/chrome-os-devices/asus-goog… Happy to test builds or offer hardware in exchange for help - I have several of these and am using the Mr Chromebox installer on them. Thanks. lspci: 00:00.0 Host bridge: Intel Corporation Device 5914 (rev 08) 00:02.0 VGA compatible controller: Intel Corporation Device 5917 (rev 07) 00:04.0 Signal processing controller: Intel Corporation Device 1903 (rev 08) 00:08.0 System peripheral: Intel Corporation Sky Lake Gaussian Mixture Model 00:14.0 USB controller: Intel Corporation Device 9d2f (rev 21) 00:14.2 Signal processing controller: Intel Corporation Device 9d31 (rev 21) 00:15.0 Signal processing controller: Intel Corporation Device 9d60 (rev 21) 00:15.2 Signal processing controller: Intel Corporation Device 9d62 (rev 21) 00:17.0 SATA controller: Intel Corporation Device 9d03 (rev 21) 00:19.0 Signal processing controller: Intel Corporation Device 9d66 (rev 21) 00:19.1 Signal processing controller: Intel Corporation Device 9d65 (rev 21) 00:1c.0 PCI bridge: Intel Corporation Device 9d12 (rev f1) 00:1c.3 PCI bridge: Intel Corporation Device 9d13 (rev f1) 00:1e.0 Signal processing controller: Intel Corporation Device 9d27 (rev 21) 00:1e.2 Signal processing controller: Intel Corporation Device 9d29 (rev 21) 00:1e.6 SD Host controller: Intel Corporation Device 9d2d (rev 21) 00:1f.0 ISA bridge: Intel Corporation Device 9d4e (rev 21) 00:1f.2 Memory controller: Intel Corporation Device 9d21 (rev 21) 00:1f.3 Multimedia audio controller: Intel Corporation Device 9d71 (rev 21) 00:1f.4 SMBus: Intel Corporation Device 9d23 (rev 21) 00:1f.5 Non-VGA unclassified device: Intel Corporation Device 9d24 (rev 21) 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) 02:00.0 Network controller: Intel Corporation Wireless 7265 (rev 59)

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flashrom dev meeting notes 27.06.2024
by Anastasia Klimchuk 02 Jul '24

02 Jul '24

# 27th June 2024, 6:00-7:00 UTC+0 https://ticket.coreboot.org/issues/542 https://ticket.coreboot.org/issues/543 https://ticket.coreboot.org/issues/545 Attendees: Joursoir, Anastasia ## Agenda * As the time goes, chip vendors are producing newer models, which sometimes re-use model IDs of old versions. Old versions are considered as "end of life", and replaced with newer models with more features. However flashchips.c accumulates everything and with time we get more and more duplicate model IDs. This makes adding new models harder, but also increases the chance users need to manually specify the chip model. Question: How can we avoid old chip models dragging down adding new ones, without completely removing them from the database (some users might still be using end-of-life chips)? * probably wasn't an issue 20 years ago when flashchips.c was designed, but now it is * have a flag "end of life" for chip definition? by default, given multiple definitions of the same model ID, the definition without a flag be selected? * vendors adding new model can mark old one end-of-life, in the same patch * [joursoir] It doesn't bother me. maybe it's not a big problem? but just having a flag "end-of-life" for information might be useful * need to be a good clear name, because flashrom still supports everything! * separate file flashchips_legacy.c for old chips? * bad: moving definitions from one file to another is pita * CONCLUSION: maybe we can add a flag to flashchip struct and no changes to probing logic yet. * ticket: [https://ticket.coreboot.org/issues/542](https://ticket.coreboot.org/issues/… * non-SPI chips are rarely used, and need special treatment in many places in the code. The code for non-SPI (flashchips definitions, parallel programmers, pieces of core logic) hasn't been updated or maintained for many years, So there are no new chips added or new features to the programmers. * maybe we can create a separate repo "flashrom-non-spi" with all the code. it will probably have 1 commit a year, or even less. The rest of code (SPI and PROG) will be simplified, better tested and can add new modern features * it will be too confusing for users, they might not know what they have, SPI or not * two binaries is confusing too * CONCLUSION: this idea is too wild, don't do this * [joursoir] It would be nice to have a pretty table of supported chips (like we had on the old wiki) on our website. Right now, there's flashrom option that prints chips in html format, however we need to rewrite it to rst so sphinx can use it. are there any pitfalls? * we can do 2-step process: one step generates .rst file (logic can be based on print.c), second step is normal build with documentation, and sphinx will generate html file for the website. * we can generate and publish html page with supported devices for the latest release. * developers who are interested what is supported at head, can look into source code or run `flashrom -L` . no need to generate html between releases. * [joursoir] I will do it! * ticket: [https://ticket.coreboot.org/issues/543](https://ticket.coreboot.org/issues/… * How about, we split our large file flashchips.c into smaller files, per manufacturer? * seems like a good idea * smaller files can get different maintainers per file => easier to get attention to your patch for flashchip * less merge conflicts * easier to find chips, easier to maintain * for example, const struct flashchip flashchips[] = { #include "chips/gigadevice.inc" #include "chips/macronix.inc" #include "chips/winbond.inc" } .inc is not valid c file, just a piece of code (slice array) another idea can be array of .c files * ticket: [https://ticket.coreboot.org/issues/545](https://ticket.coreboot.org/issues/… -- Anastasia.

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FCH device found but SMBus revision 0x71 does not match known values
by tihmstar 25 Jun '24

25 Jun '24

Hi i have a QNAP TS-H1677AXU-RP-R7-32G NAS and i'm running a very unsupported config. I installed my own linux on it and somehow managed to enable secureboot, even though the bios doesn't have any settings regarding that. I would like to also enable TPM (from my understanding the installed AMD Ryzen 7 7700 should have fTPM?), but BIOS doesn't have any options about that either. It's weird, because the mainboard even has a dedicated TPM slot for external TPM. On further research i found this article https://ristovski.github.io/posts/inside-insydeh2o/ mentioning flashrom tool for dumping bios. I tried it but no success. It did say to send you an email, so here you go. Maybe you can help me with my journey to dump my bios? If nothing else, maybe the attached log is helpful to you. Cheers tihmstar

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FAILED: juniper router
by Steve Topletz 25 Jun '24

25 Jun '24

I have previously backed up the bios and am attempting to erase it, and am left in an "unknown" state. My desire is to successfully execute the erase. I am constrained from physically disassembling the mx204 router to confirm the board and chip. Multiple flash chip definitions match the detected chip(s): "MX25L12805D", "MX25L12833F", "MX25L12835F/MX25L12873F", "MX25L12845E/MX25L12865E", "MX25L12850F" I tried doing wp-status on all of them, and all responded "Cannot read SECURITY: unsupported by chip" except for "MX25L12850F" which responded: Protection range: start=0x00000000 length=0x00000000 (none) Protection mode: disabled node:/var/tmp/fw/x86_64-linux-gnu/sbin# ./flashrom -p internal:laptop=this_is_not_a_laptop -c "MX25L12850F" --ifd -i bios --erase -noverify-all --force -V flashrom 1.4.0-devel on Linux 5.2.60-rt15-LTS19 (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with GCC 12.2.0, little endian Command line (11 args): ./flashrom -p internal:laptop=this_is_not_a_laptop -c MX25L12850F --ifd -i bios --erase -noverify-all --force -V Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. No DMI table found. Found chipset "Intel C610/X99 (Wellsburg)" with PCI ID 8086:8d44. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc01: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (unknown) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x22: BIOS Lock Enable: enabled, BIOS Write Enable: disabled Warning: BIOS region SMM protection is enabled! Warning: Setting BIOS Control at 0xdc from 0x22 to 0x01 failed. New value is 0x22. SPIBAR = 0x00007fa5f44f1000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x50: 0x00007a5b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x7a, BRRA 0x5b 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0fff0800 FREG1: BIOS region (0x00800000-0x00ffffff) is read-write. 0x5C: 0x07ff0003 FREG2: Management Engine region (0x00003000-0x007fffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. 0x74: 0x8fff0de0 PR0: Warning: 0x00de0000-0x00ffffff is read-only. 0x78: 0x8dab0dab PR1: Warning: 0x00dab000-0x00dabfff is read-only. 0x7C: 0x8da30d80 PR2: Warning: 0x00d80000-0x00da3fff is read-only. 0x80: 0x8cfe0820 PR3: Warning: 0x00820000-0x00cfefff is read-only. 0x84: 0x80000000 PR4: Warning: 0x00000000-0x00000fff is read-only. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84150 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=5, DBC=1, SME=0, SCF=0 0x94: 0x0606 (PREOP) 0x96: 0xf27c (OPTYPE) 0x98: 0x0002209f (OPMENU) 0x9c: 0x00000503 (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x80802015 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=1, EO=0x20, VCL=1 0xc8: 0x00002015 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=1, EO=0x20 0xd0: 0x50444653 (FPB) OK. ======================================================================== You may be running flashrom on an unknown laptop. We could not detect this for sure because your vendor has not set up the SMBIOS tables correctly. Some internal buses have been disabled for safety reasons. You can enforce using all buses by adding -p internal:laptop=this_is_not_a_laptop to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and https://flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== The following protocols are supported: FWH, SPI. Probing for Macronix MX25L12850F, 16384 kB: compare_id: id1 0xc2, id2 0x2018 Added layout entry 00000000 - 00ffffff named complete flash Found Macronix flash chip "MX25L12850F" (16384 kB, SPI) mapped at physical address 0x00000000ff000000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Skipping writeprotect-based unlocking for read/verify operations. Reading ich descriptor... read_flash: region (00000000..0xffffff) is readable, reading range (00000000..0x000fff). done. Added layout entry 00000000 - 00000fff named fd Added layout entry 00800000 - 00ffffff named bios Added layout entry 00003000 - 007fffff named me Added layout entry 00001000 - 00002fff named gbe Using region: "bios". spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. erase_write: region (00000000..0xffffff) is writable, erasing range (0x800000..0x800fff). Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=1, DBC=0, SME=0, SCF=0 Running OPCODE 0x20 failed at address 0x800000 (payload length was 0). spi_write_cmd failed during command execution at address 0x800000 Erase/write done from 800000 to ffffff Erase Failedspi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 5 not supported by programmer. wp_read_register: read from register 5 not is supported by programmer, writeprotect operations will assume it contains 0x00. Your flash chip is in an unknown state. Get help on IRC (see https://www.flashrom.org/Contact) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"!------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0x7fa5f44f48a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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