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[PATCH] Intel Poulsbo chipset support
by Adam Jurkowski 21 Dec '09

21 Dec '09

Add support for Intel Poulsbo chipset. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl>

3 6

ECS K7SOM+ motherboard
by Charles M 21 Dec '09

21 Dec '09

We semi-frequently see these ECS K7SOM+ motherboards and usually end up tossing them because the CPU soldered to the motherboard. The ECS web site dynamically generates pages but the manual still appears if you select Motherboard > Onboard and the K7SOM+. I've attached the flashrom, lspci and superiotool output. If anyone has further questions about the motherboard please email me directly and I'll investigate further. Charles McColm

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Acer Ali 1631
by Charles M 21 Dec '09

21 Dec '09

This motherboard came to us in a beige box, so I can't comment on the particular model of motherboard. It shows as an Acer Ali 1631 as the Motherboard Model and Hsing Tech Enterprises as the motherboard OEM. Cheers, Charles

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Intel D850GB "Intel Desktop Board"
by Charles M 21 Dec '09

21 Dec '09

The Intel D850GB has the words "Intel Desktop Board" imprinted on the motherboard, but it's pretty far from being a general user desktop motherboard. It sports 4 RAMBUS 600/800 slots and what looks to be a non-standard connector for power button and LEDs (but most cases could be rigged to fit). This motherboard is a single CPU Socket 423 motherboard. The manual can be found: http://www.intel.com/support/motherboards/desktop/d850gb/sb/cs-013247.htm If anyone has further questions about the motherboard please email me directly and I'll investigate further. Cheers, Charles

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[PATCH] Boards: Fix several issues with nvidia_mcp_gpio_set.
by Luc Verhaegen 21 Dec '09

21 Dec '09

- CK804, MCP04, MCP2 use the isa bridges.. - Newer nvidia mcp's do use the smbus controllers (Found by Michael Karcher). - gpio line check breaks EPoX EP-8RDA3+, and should be wider. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index 8b5ed95..2c58927 100644 --- a/board_enable.c +++ b/board_enable.c @@ -440,20 +440,30 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) uint16_t base; uint8_t tmp; - if ((gpio < 0) || (gpio > 31)) { + if ((gpio < 0) || (gpio > 0x40)) { fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + /* First, check the ISA Bridge */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: - fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); + /* Newer MCPs use the SMBus Controller */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0264: /* MCP51 */ + break; + default: + fprintf(stderr, + "\nERROR: no nVidia LPC/SMBus controller found.\n"); return -1; + } + break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ -- 1.6.0.2 --lrZ03NoBR/3+SXJZ--

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Board enable requested
by Bill Maidment 21 Dec '09

21 Dec '09

Hello there. My motherboard is a Gigabyte GA-M51GM-S2G no version number apparent. The requested diagnostics are attached. BIOS downloads are available from http://www.giga-byte.com/Support/Motherboard/BIOS_Model.aspx?ProductID=2281 Please let me know when the board enable patch is available. Many thanks for the excellent service. Regards Bill -- Bill Maidment Maidment Enterprises Pty Ltd www.maidment.vu Consultant to Elgas Ltd Phone: 02 9904 3364

3 2

ASUS CUV4X-C
by Charles M 21 Dec '09

21 Dec '09

The ASUS CUV4X comes in a few varieties that our Computer Refurbishing project sees. This one is the -C version. Asus uses dynamic pages to distribute manuals, etc., and the manual from this baby can be found at http://support.asus.com/. This board is a socket 370 (Pentium III/Celeron) motherboard. If more data is required please email me and I can look into detailing the system more. (see attached flashrom,lspci,superiotools info). Charles McColm

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[commit] r809 - trunk
by svn＠flashrom.org 21 Dec '09

21 Dec '09

Author: libv Date: 2009-12-21 16:30:46 +0100 (Mon, 21 Dec 2009) New Revision: 809 Modified: trunk/chipset_enable.c Log: Chipset: Add support for Intel Poulsbo chipset. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-12-18 08:37:55 UTC (rev 808) +++ trunk/chipset_enable.c 2009-12-21 15:30:46 UTC (rev 809) @@ -5,6 +5,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger + * Copyright (C) 2009 Kontron Modular Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -391,6 +392,26 @@ return enable_flash_ich(dev, name, 0xdc); } +static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) +{ + uint16_t old, new; + int err; + + if ((err = enable_flash_ich(dev, name, 0xd8)) != 0) + return err; + + old = pci_read_byte(dev, 0xd9); + printf_debug("BIOS Prefetch Enable: %sabled, ", + (old & 1) ? "en" : "dis"); + new = old & ~1; + + if (new != old) + pci_write_byte(dev, 0xd9, new); + + return 0; +} + + #define ICH_STRAP_RSVD 0x00 #define ICH_STRAP_SPI 0x01 #define ICH_STRAP_PCI 0x02 @@ -1155,6 +1176,7 @@ {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */

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Fail to flash BIOS under ICH9R with descriptor mode
by eugenehsu 21 Dec '09

21 Dec '09

Hi I used the flashrom with SB ICH9R and flash chip SST SST25VF016B, and the descriptor mode is activated. The software version is flashrom-0.9.1 and pciutils-3.1.4. I failed to flash the BIOS. Please refer to the messages: =========================== DiskStation> ./flashrom -E flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x001fffff: 0x3000 ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x00 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! =========================== BTW, please find the "flashrom -E -V" messages in the attachment. Do you know how to solve this problem ? Thanks for your help. Eugene

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[PATCH] Board: Add Gigabyte M51GM.
by Luc Verhaegen 21 Dec '09

21 Dec '09

The board ids match the M55Plus, but guess what, they require the same board enable ;) Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index 8b5ed95..91d27ac 100644 --- a/board_enable.c +++ b/board_enable.c @@ -445,11 +445,12 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { - case 0x0030: /* CK804 */ - case 0x0050: /* MCP04 */ + case 0x0030: /* MCP04 */ + case 0x0050: /* CK804 */ case 0x0060: /* MCP2 */ + case 0x0260: /* MCP51 */ break; default: fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); @@ -494,6 +495,14 @@ static int nvidia_mcp_gpio31_raise(const char *name) } /** + * Suited for Gigabyte GA-M51GM-S2G: nVidia MCP51. + */ +static int nvidia_mcp_gpio3B_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x3B, 0x01); +} + +/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -1251,6 +1260,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, + {0x10DE, 0x02FA, 0x1458, 0x5000, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, "GIGABYTE", "GA-M51GM/M55plus", nvidia_mcp_gpio3B_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, -- 1.6.0.2 --AhhlLboLdkugWU4S--

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