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Bios Update
by Bruno Vaillancourt 22 Dec '09

22 Dec '09

Trying to flash my bios and I get this message any idea what is the problem bruno@bruno-desktop:~/Desktop/BiosUpdate$ sudo flashrom -w A8N321303.ROM flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "Winbond W39V080A" (1024 KB, LPC) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000008! Expected=0xff, Read=0x10, failed byte count from 0x00000000-0x000fffff: 0x8b465 ERASE FAILED! ERASE FAILED! FAILED!

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[commit] r811 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: hailfinger Date: 2009-12-22 14:04:53 +0100 (Tue, 22 Dec 2009) New Revision: 811 Modified: trunk/flash.h Log: Clarify comment about how to enter chip erase functions in struct block_eraser. Reported by Sean Nelson. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-12-22 13:04:13 UTC (rev 810) +++ trunk/flash.h 2009-12-22 13:04:53 UTC (rev 811) @@ -174,8 +174,8 @@ int (*erase) (struct flashchip *flash); /* - * Erase blocks and associated erase function. The default entry is a - * chip-sized virtual block together with the chip erase function. + * Erase blocks and associated erase function. Any chip erase function + * is stored as chip-sized virtual block together with said function. */ struct block_eraser { struct eraseblock{

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[commit] r810 - trunk
by svn＠flashrom.org 22 Dec '09

22 Dec '09

Author: libv Date: 2009-12-22 14:04:13 +0100 (Tue, 22 Dec 2009) New Revision: 810 Modified: trunk/board_enable.c Log: Boards: Fix several issues with nvidia_mcp_gpio_set. - CK804, MCP04, MCP2 use the isa bridges.. - Newer nvidia mcp's do use the smbus controllers (Found by Michael Karcher). - gpio line check breaks EPoX EP-8RDA3+, and should be wider. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-21 15:30:46 UTC (rev 809) +++ trunk/board_enable.c 2009-12-22 13:04:13 UTC (rev 810) @@ -440,20 +440,30 @@ uint16_t base; uint8_t tmp; - if ((gpio < 0) || (gpio > 31)) { + if ((gpio < 0) || (gpio >= 0x40)) { fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); return -1; } - dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + /* First, check the ISA Bridge */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ case 0x0050: /* MCP04 */ case 0x0060: /* MCP2 */ break; default: - fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); + /* Newer MCPs use the SMBus Controller */ + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0264: /* MCP51 */ + break; + default: + fprintf(stderr, + "\nERROR: no nVidia LPC/SMBus controller found.\n"); return -1; + } + break; } base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */

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Re: [flashrom] Is K7S6A supported by flashrom?
by Carl-Daniel Hailfinger 22 Dec '09

22 Dec '09

Hi Dave, On 19.12.2009 20:11, spirals wrote: > [...] no effect on my problem o/p when flashing my BIOS remains : > flashrom v0.9.1-r792 > No coreboot table found. > Found chipset "SiS 745", enabling flash write... FAILED! > This chipset supports the following protocols: Non-SPI. > Disabling flash write protection for board "Elitegroup K7S6A"... OK. > Calibrating delay loop... OK. > Found chip "SST SST39SF020A" (256 KB, Parallel) at physical address > 0xfffc0000. > > [...] patch is in but I still get Found chipset "SiS 745", enabling > flash write... FAILED! so write enable is NOT working. Brain is > slightly addled, (dja.) spirals. thanks for the report. I admit that the message is confusing. "enabling flash write... FAILED" does not mean that write enable failed, it just means that at least one of the expectations of the chipset write enable function was violated. And yes, we should fix that up. The problem is that we don't have any docs for this chipset and the code was just a guess. However, board the flash write enable function works fine as you can see from looking at the output: The flash chip is now found and it wasn't found before. > Carl-Daniel Hailfinger wrote: >> On 08.12.2009 11:41, Luc Verhaegen wrote: >>> http://patchwork.coreboot.org/patch/635/ >> >> And committed in r808 with some modifications. Unless you have problems writing to the chip, I think everything is OK. Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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Re: [flashrom] (update, update) Gigabyte GA-7ZXE v1.1
by Charles M 22 Dec '09

22 Dec '09

Oops, my bad, I was pretty sure the VIA chip was the Southbridge but I questioned my own logic when I saw it listed as a super i/o chip in the manual: Chipset: VT82C686B PCI Super-I/O Integrated Peripheral Controller (PSIPC) There's a chip just under the tail of the AGP slot that might be the super i/o chip... it's an ICS 94236AF but this is listed as the clock generator... So where is the super i/o chip usually located?

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[PATCH] Superiotool: Add VT82C686
by Carl-Daniel Hailfinger 22 Dec '09

22 Dec '09

Add VIA VT82C686A/VT82C686B support to superiotool. The patch as-is will likely not detect the Super I/O due to missing PCI functionality in superiotool, but you might get lucky. This adds an additional requirement to superiotool: libpci. I have made the PCI code conditional on PCI_SUPPORT for now. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: superiotool-vt82c686/via.c =================================================================== --- superiotool-vt82c686/via.c (Revision 0) +++ superiotool-vt82c686/via.c (Revision 0) @@ -0,0 +1,112 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" +#ifdef PCI_SUPPORT +#include <pci/pci.h> +#endif + +#define DEVICE_ID_VT82C686_REG 0xe0 + +#define DEVICE_REV_VT82C686_REG 0xe1 + +static const struct superio_registers reg_table[] = { + {0x3c, "VT82C686A/VT82C686B", { + {EOT}}}, + {EOT} +}; + +#ifdef PCI_SUPPORT +static uint8_t vt82c686_conf = 0; +#endif + +static int enter_conf_mode_via_vt82c686(void) +{ +#ifdef PCI_SUPPORT + struct pci_dev *dev; + + dev = pci_dev_find(0x1106, 0x0686); + if (!dev) { + if (verbose) + printf("Associated PCI device not found.\n"); + return 1; + } + vt82c686_conf = pci_read_byte(dev, 0x85); + if (verbose) + printf("Super I/O %sabled, Super I/O configuration %sabled", + (vt82c686_conf & (1 << 0)) ? "en" : "dis", + (vt82c686_conf & (1 << 1)) ? "en" : "dis"); + /* If Super I/O is not enabled, skip it. */ + if (!(vt82c686_conf & (1 << 0))) + return 1; + /* Enable Super I/O configuration mode. */ + pci_write_byte(dev, 0x85, vt82c686_conf | (1 << 1)); +#endif + return 0; +} + +static void exit_conf_mode_via_vt82c686(void) +{ +#ifdef PCI_SUPPORT + struct pci_dev *dev; + + dev = pci_dev_find(0x1106, 0x0686); + if (!dev) { + printf("Bug: PCI device 0x%04x:0x%04x not found during " + "shutdown. Please report to coreboot(a)coreboot.org\n"); + return; + } + /* Restore (disable?) Super I/O configuration mode setting. */ + pci_write_byte(dev, 0x85, vt82c686_conf); +#endif +} + +void probe_idregs_via(uint16_t port) +{ + uint16_t id; + uint8_t rev; + + probing_for("VIA", "", port); + + if (enter_conf_mode_via_vt82c686()) + return; + + id = regval(port, DEVICE_ID_VT82C686_REG); + + rev = regval(port, DEVICE_REV_VT82C686_REG); + + if (superio_unknown(reg_table, id)) { + if (verbose) + printf(NOTFOUND "id=0x%04x, rev=0x%02x\n", id, rev); + exit_conf_mode_via_vt82c686(); + return; + } + + printf("Found VIA %s (id=0x%04x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, id), id, rev, port); + chip_found = 1; + + exit_conf_mode_via_vt82c686(); +} + +void print_via_chips(void) +{ + print_vendor_chips("VIA", reg_table); +} Index: superiotool-vt82c686/superiotool.h =================================================================== --- superiotool-vt82c686/superiotool.h (Revision 4988) +++ superiotool-vt82c686/superiotool.h (Arbeitskopie) @@ -141,6 +141,10 @@ void probe_idregs_winbond(uint16_t port); void print_winbond_chips(void); +/* via.c */ +void probe_idregs_via(uint16_t port); +void print_via_chips(void); + /** Table of which config ports to probe for each Super I/O family. */ static const struct { void (*probe_idregs) (uint16_t port); @@ -153,6 +157,7 @@ {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, + {probe_idregs_via, {0x3f0, EOT}}, }; /** Table of functions to print out supported Super I/O chips. */ @@ -165,6 +170,7 @@ {print_nsc_chips}, {print_smsc_chips}, {print_winbond_chips}, + {print_via_chips}, }; #endif Index: superiotool-vt82c686/Makefile =================================================================== --- superiotool-vt82c686/Makefile (Revision 4988) +++ superiotool-vt82c686/Makefile (Arbeitskopie) @@ -32,7 +32,7 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o via.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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Verbose output of lspci, superiotool and flashrom - Asus A7V (unsupported)
by Adrian Glaubitz 21 Dec '09

21 Dec '09

Hi there, just tried to flash an old ASUS A7V with flashrom r809. The flash chip is not detected at all, I presume the reason being that the flash chip is not yet supported by flashrom. The chip reads: Mosel Vitelic V29C51002T: <http://www.datasheetcatalog.com/datasheets_pdf/V/2/9/C/V29C51002T.shtml> Please find the output of lspci -nnvvvxxx, flashrom -V and superiotool -dV attached. Regards, Adrian

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HP Compaq d530 CMT
by Charles M 21 Dec '09

21 Dec '09

This is the flashrom, lspci and superiotool information from a HP branded (Compaq) d530 CMT tower. I didn't crack the case to see what motherboard was inside because the machine is in active use. Cheers Charles

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Gigabyte 7ZXE Rev 1.0
by Charles M 21 Dec '09

21 Dec '09

Here's the flashrom, lspci and superiotool information for the Gigabyte 7ZXE motherboard. From Gigabytes web site it looks like there have been at least a couple of revisions of this motherboard. This is revision 1.0. The link to Gigabyte's information on this site is: http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI… Cheers, Charles

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MSI KM2M Combo
by Charles M 21 Dec '09

21 Dec '09

The MSI KM2M Combo is a Socket A (462) motherboard that sports 2 SDRAM and 2 DDR-SDRAM memory slots, 3 PCI slots and 1 AGP slot. I've attached the flashrom,lspci, and superiotool information for this board. Cheers, Charles

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