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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

Somewhat strage: After flashing the old bios with the suggested patch I got the following error output: flashrom v0.9.1-r845 No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... done. COMPLETE. Verifying flash... VERIFY FAILED at 0x00010058! Expected=0x15, Read=0x05, failed byte count from 0x00000000-0x001fffff: 0x12d075 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! A verification by reading the BIOS (via flashrom -r <file>) and comparing it with the original bios (via diff) shows the same difference. Best, Parallix

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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

Dear Carl-Daniel (Hailfinger), dear Michael (Karcher) here comes the information of the HP Compaq 615 you asked for. Best, Parallix

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Re: [flashrom] Big problem after flash of SST SST25VF016B on HP Compaq 615
by Michael Karcher 09 Jan '10

09 Jan '10

Am Samstag, den 09.01.2010, 20:00 +0100 schrieb Parallix: > should I now flash the old (and buggy) bios or the new (hopefully bugless) > one? The old one, to recover your system to a safe state. Fixing the real issue is left for later. You might want to compare whether the last 256KB of the old and new BIOS are the same. In that case, an update without removing the boot block lock is possible, although not yet implemented in flashrom (partial write). > Should I use the trunk/developers version of flashrom or the released > one? You should use the developers version with the suggested modification applied. Please also send the info Carl-Daniel Hailfinger requested. Regards, Michael Karcher

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Big problem after flash of SST SST25VF016B on HP Compaq 615
by Parallix 09 Jan '10

09 Jan '10

I've a big problem. Of course, I made a backup of my old bios with flashrom -r oldbios.bin. Then I tried to flash my HP Compaq 615 with flashrom v0.9.1-r792 and got the following "warning": No coreboot table found. Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... Erasing flash chip... ERASE FAILED at 0x001c0000! Expected=0xff, Read=0xfc, failed byte count from 0x00000000-0x001fffff: 0x37386 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! After reading the flash contents with flashrom -r newbios.bin I compared the old bios with the new one. They differ. What can I now do? Best, Parallix

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Re: [flashrom] [commit] r845 - trunk
by Luc Verhaegen 09 Jan '10

09 Jan '10

On Sat, Jan 09, 2010 at 06:36:07PM +0100, svn(a)flashrom.org wrote: > Author: mkarcher > Date: 2010-01-09 18:36:06 +0100 (Sat, 09 Jan 2010) > New Revision: 845 > > Modified: > trunk/board_enable.c > Log: > Enable flashing on MSI 651M-L. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Sergey Lichack <shadowpilot34(a)gmail.com> I seem unable to find the prerequisites for supporting this board on the ml, lspci and superio. The superio one is very important, as i need to know which superio this is for the upcoming superio changes. I expect it to be a w83697(T)HF, as so far only those required this memw enable (like the it8705 is the only one require something rather similar). But cool, we have our first sis gpio poker. > +/** > + * Enable some GPIO pin on SiS southbridge. > + * Suited for MSI 651M-L: SiS651 / SiS962 > + */ > +static int board_msi_651ml(const char *name) > +{ > + struct pci_dev *dev; > + uint16_t base; > + uint16_t temp; > + > + dev = pci_dev_find(0x1039, 0x0962); > + if (!dev) { > + fprintf(stderr, "Expected south bridge not found\n"); > + return 1; > + } > + > + /* Registers 68 and 64 seem like bitmaps */ > + base = pci_read_word(dev, 0x74); > + temp = INW(base + 0x68); > + temp &= ~(1 << 0); /* Make pin output? */ > + printf_debug("changed to %04x\n",temp); Where do you end up writing this bit? > + > + temp = INW(base + 0x64); > + temp |= (1 << 0); /* Raise output? */ > + OUTW(temp, base + 0x64); > + > + w836xx_memw_enable(0x2E); > + > + return 0; > +} > + One or two more of these routines, and we might make a first stab at a general sis gpio routine. Luc Verhaegen.

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Addendum: Big problem after flash of SST SST25VF016B on HP Compaq 615 (also with flashrom v0.9.1-r844)
by Parallix 09 Jan '10

09 Jan '10

I've the same problem I posted on Sat Jan 9 18:28:53 CET 2010 with flashrom v0.9.1-r844 I kindly ask for your help. Best, Parallix

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Board Enable for MSI 651M-L
by Michael Karcher 09 Jan '10

09 Jan '10

Hello, This patch should enable flash read/write on the MSI 651M-L. Please test. DuratarskeyK: This is your board. Please report success or failure (with output of "flashrom -V") to the mailing list. Regards, Michael Karcher diff --git a/board_enable.c b/board_enable.c index 39cdadc..2d3b9a1 100644 --- a/board_enable.c +++ b/board_enable.c @@ -947,6 +947,35 @@ static int board_soyo_sy_7vca(const char *name) return 0; } +/** + * Enable some GPIO pin on SiS southbridge. + * Suited for MSI 651M-L: SiS651 / SiS962 + */ +static int board_msi_651ml(const char *name) +{ + struct pci_dev *dev; + uint16_t base; + uint16_t temp; + + dev = pci_dev_find(0x1039, 0x0962); + if (!dev) { + fprintf(stderr, "Expected south bridge not found\n"); + return 1; + } + + /* Registers 68 and 64 seem like bitmaps */ + base = pci_read_word(dev, 0x74); + temp = INW(base + 0x68); + temp &= ~(1 << 0); /* Make pin output? */ + OUTW(temp, base + 0x68); + + temp = INW(base + 0x64); + temp |= (1 << 0); /* Raise output? */ + OUTW(temp, base + 0x64); + + return 0; +} + static int it8705f_write_enable(uint8_t port, const char *name) { enter_conf_mode_ite(port); @@ -1215,6 +1244,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, "MSI", "MS-7005 (651M-L)", board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise},

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Re: [flashrom] Board Enable for MSI 651M-L
by Michael Karcher 09 Jan '10

09 Jan '10

> Acked-by: Sergey Lichack <shadowpilot34(a)gmail.com> > > 2010/1/9 Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > That patch is wrong. I missed a superio enable. > > Please use the included one (also at > http://dpaste.com/142499/) instead. Thanks for your ack. Committed as revision 845. Regards, Michael Karcher

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[commit] r845 - trunk
by svn＠flashrom.org 09 Jan '10

09 Jan '10

Author: mkarcher Date: 2010-01-09 18:36:06 +0100 (Sat, 09 Jan 2010) New Revision: 845 Modified: trunk/board_enable.c Log: Enable flashing on MSI 651M-L. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sergey Lichack <shadowpilot34(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2010-01-09 14:18:01 UTC (rev 844) +++ trunk/board_enable.c 2010-01-09 17:36:06 UTC (rev 845) @@ -947,6 +947,37 @@ return 0; } +/** + * Enable some GPIO pin on SiS southbridge. + * Suited for MSI 651M-L: SiS651 / SiS962 + */ +static int board_msi_651ml(const char *name) +{ + struct pci_dev *dev; + uint16_t base; + uint16_t temp; + + dev = pci_dev_find(0x1039, 0x0962); + if (!dev) { + fprintf(stderr, "Expected south bridge not found\n"); + return 1; + } + + /* Registers 68 and 64 seem like bitmaps */ + base = pci_read_word(dev, 0x74); + temp = INW(base + 0x68); + temp &= ~(1 << 0); /* Make pin output? */ + printf_debug("changed to %04x\n",temp); + + temp = INW(base + 0x64); + temp |= (1 << 0); /* Raise output? */ + OUTW(temp, base + 0x64); + + w836xx_memw_enable(0x2E); + + return 0; +} + static int it8705f_write_enable(uint8_t port, const char *name) { enter_conf_mode_ite(port); @@ -1215,6 +1246,7 @@ {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, + {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, "MSI", "MS-7005 (651M-L)", board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise},

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Samsung R45 laptop - SAMSUNG SR45P (I guess)
by Jon Shadow 09 Jan '10

09 Jan '10

Here's the info about my laptop flashrom -V http://paste.pocoo.org/show/163671/ lspci -nnvvvxxx http://paste.pocoo.org/show/163672/ dmidecode http://paste.pocoo.org/show/163675/ superiotool -deV http://paste.pocoo.org/show/163676/ -- Sergeyli

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