The following command ran successfully on an eMachines 333cs. (I
checked that my.rom was the same as the original ROM file flashed to the
BIOS.)
flashrom -rV my.rom > flashrom.txt
The smolt URL for this machine is
http://www.smolts.org/client/show/pub_7982b3d7-a650-4770-8128-d385918bf9bd
The file flashrom.txt is attached.
Hallo Marcel,
On 19.02.2010 02:37, marcel partap wrote:
> Hallo Carl-Daniel,
> nice to see progress on newer nforce, finally the day where users can
> apply bios bugfixes without resorting to obsolete disk operating
> systems disks are near - woohoo!! ;)
> guess it indeed does use SPI, hope you can figure something out from
> this log.
Thank you for the log. It definitely helps us a lot.
> flashrom v0.9.1-runknown
>
Probably r906 (in case someone looks at this …
[View More]report later on).
> No coreboot table found.
> DMI string 0: "ECS"
> DMI string 1: "GeForce 8000 series"
> DMI string 2: "1.0 "
> DMI string 3: "ECS"
> DMI string 4: "GeForce 8000 series"
> DMI string 5: "1.0 "
> Found chipset "NVIDIA MCP78S", enabling flash write...
> This chipset is not really supported yet. Guesswork...
> ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0
> Guessed flash bus type is SPI
> Found SMBus device 10de:0752 at 00:01:1
> SPI BAR is at 0xf9e80000, after clearing low bits BAR is at 0xf9e80000
> Mapping MCP67 SPI at 0xf9e80000, unaligned size 0x544.
> SPI control is 0xc01a, enable=0, idle=0
> SPI on this chipset is not supported yet.
> OK.
> This chipset supports the following protocols: None.
>
And more confirmation that the code so far works fine.
I hope to find some time to work on full SPI support around mid April.
Regards,
Carl-Daniel
--
"I do consider assignment statements and pointer variables to be among
computer science's most valuable treasures."
-- Donald E. Knuth
[View Less]
Here's a very quick patch to fix the missing unlock code.
Fixes missing unlock for certain chips:
* unlock_49lf00x
* Pm49fl002
* Pm49fl004
* unlock_49flxxxc
* SST49LF160C
* unlock_winbond_fwhub
* W39V080FA
* W39V080FA (dual mode)
Fixes missing printlock for certain chip:
* printlock_w39v040c
* W39V040C
Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>
---
Let's get this regression fixed ASAP.
Dear reader,
my Asus m2n-mx motherboard seems not supported by Flashrom. The
w39v040c was not found automatically, so I tried a forced read.
The flashrom dump and the original bios are very similar but not the
same. In case you want to have a look at the dump, I included a link
to the file. If you need extra information, please let me know.
Ted Crilly
Motherboard:
Asus m2n-mx rev. 1.06G
Flashrom (visual inspection):
Winbond PLCC32
w39v040cpz
4548323002
632fafa
SuperIO (visual …
[View More]inspection):
ITE
it8712f-s
0714-kxs
zm2s50 L
BIOS:
(Bios version 1004 adds protection from downgrading BIOS version)
ftp://ftp.asus.com/pub/ASUS/mb/socketAM2/M2N-MX/M2NX1004.zip
DUMPED BIOS forced read:
(flashrom -f -r -c W39V040C m2n-mx.bios1004_dump)
http://datastructuur.nl/flashrom/m2n-mx.bios1004_dump
[View Less]
Refactor MCP SPI detection:
- Set supported buses based on ISA bridge reg 0x8a
- Use MCP55 chipset enable only if LPC is detected
- Allow LPC on MCP61
- Eliminate duplicated code where possible
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-mcp_spi_detect_refactor/chipset_enable.c
===================================================================
--- flashrom-mcp_spi_detect_refactor/chipset_enable.c (Revision 905)
+++ flashrom-…
[View More]mcp_spi_detect_refactor/chipset_enable.c (Arbeitskopie)
@@ -1054,30 +1054,39 @@
return 0;
}
-/**
- * The MCP67 code is guesswork based on cleanroom reverse engineering.
- * Due to that, it only reads info and doesn't change any settings.
- * It is assumed that LPC chips need the MCP55 code and SPI chips need the
- * code provided in this function. Until we know for sure, call
- * enable_flash_mcp55 from this function. Warning: enable_flash_mcp55
- * might make SPI flash inaccessible. The same caveat applies to SPI init
- * for LPC flash.
+/* This is a shot in the dark. Even if the code is totally bogus for some
+ * chipsets, users will at least start to send in reports.
*/
-static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
+static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
{
- int result = 0;
uint8_t byte;
uint16_t status;
+ char *busname;
uint32_t mcp_spibaraddr;
void *mcp_spibar;
struct pci_dev *smbusdev;
+ msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
+
/* dev is the ISA bridge. No idea what the stuff below does. */
byte = pci_read_byte(dev, 0x8a);
- msg_pdbg("ISA bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 is "
- "%i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
- msg_pdbg("Guessed flash bus type is %s\n", ((byte >> 5) & 0x3) == 0x2 ?
- "SPI" : "unknown, probably LPC");
+ msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
+ "is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
+ switch ((byte >> 5) & 0x3) {
+ case 0x0:
+ buses_supported = CHIP_BUSTYPE_LPC;
+ break;
+ case 0x2:
+ buses_supported = CHIP_BUSTYPE_SPI;
+ break;
+ default:
+ buses_supported = CHIP_BUSTYPE_UNKNOWN;
+ break;
+ }
+ busname = flashbuses_to_text(buses_supported);
+ msg_pdbg("Guessed flash bus type is %s\n", busname);
+ free(busname);
+
/* Disable the write code for now until we have more info. */
#if 0
byte |= (1 << 6);
@@ -1088,8 +1097,9 @@
/* Look for the SMBus device (SMBus PCI class) */
smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
if (!smbusdev) {
- msg_perr("ERROR: SMBus device not found. Aborting.\n");
- exit(1);
+ msg_perr("ERROR: SMBus device not found.\n");
+ buses_supported = CHIP_BUSTYPE_NONE;
+ return 1;
}
msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
smbusdev->vendor_id, smbusdev->device_id,
@@ -1108,7 +1118,7 @@
msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
/* Accessing a NULL pointer BAR is evil. Don't do it. */
- if (mcp_spibaraddr) {
+ if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
/* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
@@ -1125,54 +1135,81 @@
status, status & 0x1, (status >> 8) & 0x1);
/* FIXME: Remove the physunmap once the SPI driver exists. */
physunmap(mcp_spibar, 0x544);
+ } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
+ msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
+ buses_supported &= ~CHIP_BUSTYPE_SPI;
+ } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
+ msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
+ " doesn't support SPI.\n");
} else {
- msg_pdbg("Strange. MCP67 SPI BAR is invalid.\n");
+ msg_pdbg("MCP SPI not used.\n");
}
msg_pinfo("Please send the output of \"flashrom -V\" to "
"flashrom(a)flashrom.org to help us finish support for your "
"chipset. Thanks.\n");
- /* Not sure if this is still correct. No docs as usual. */
- result = enable_flash_mcp55(dev, name);
+ return 0;
+}
+/**
+ * The MCP67 code is guesswork based on cleanroom reverse engineering.
+ * Due to that, it only reads info and doesn't change any settings.
+ * It is assumed that LPC chips need the MCP55 code and SPI chips need the
+ * code provided in this function. Until we know for sure, call
+ * enable_flash_mcp55 from this function. Warning: enable_flash_mcp55
+ * might make SPI flash inaccessible. The same caveat applies to SPI init
+ * for LPC flash.
+ */
+static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
+{
+ int result = 0;
+
+ result = enable_flash_mcp6x_7x_common(dev, name);
+ if (result)
+ return result;
+
+ /* Not sure if this is correct. No docs as usual. */
+ switch (buses_supported) {
+ case CHIP_BUSTYPE_LPC:
+ result = enable_flash_mcp55(dev, name);
+ break;
+ case CHIP_BUSTYPE_SPI:
+ msg_pinfo("SPI on this chipset is not supported yet.\n");
+ buses_supported = CHIP_BUSTYPE_NONE;
+ break;
+ default:
+ msg_pinfo("Something went wrong with bus type detection.\n");
+ buses_supported = CHIP_BUSTYPE_NONE;
+ break;
+ }
+
return result;
}
-/* This is a shot in the dark. Even if the code is totally bogus for some
- * chipsets, users will at least start to send in reports.
- */
static int enable_flash_mcp7x(struct pci_dev *dev, const char *name)
{
- uint8_t byte;
- uint32_t mcp_spibaraddr;
- struct pci_dev *smbusdev;
+ int result = 0;
- msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
+ result = enable_flash_mcp6x_7x_common(dev, name);
+ if (result)
+ return result;
- /* dev is the ISA bridge. No idea what the stuff below does. */
- byte = pci_read_byte(dev, 0x8a);
- msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
- "is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
-
- /* Look for the SMBus device (SMBus PCI class) */
- smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
- if (!smbusdev) {
- msg_perr("ERROR: SMBus device not found. Aborting.\n");
- exit(1);
+ /* Not sure if this is correct. No docs as usual. */
+ switch (buses_supported) {
+ case CHIP_BUSTYPE_LPC:
+ msg_pinfo("LPC on this chipset is not supported yet.\n");
+ break;
+ case CHIP_BUSTYPE_SPI:
+ msg_pinfo("SPI on this chipset is not supported yet.\n");
+ buses_supported = CHIP_BUSTYPE_NONE;
+ break;
+ default:
+ msg_pinfo("Something went wrong with bus type detection.\n");
+ buses_supported = CHIP_BUSTYPE_NONE;
+ break;
}
- msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
- smbusdev->vendor_id, smbusdev->device_id,
- smbusdev->bus, smbusdev->dev, smbusdev->func);
- /* Locate the BAR where the SPI interface lives. */
- mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
- msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
-
- msg_pinfo("Please send the output of \"flashrom -V\" to "
- "flashrom(a)flashrom.org to help us finish support for your "
- "chipset. Thanks.\n");
-
- return 0;
+ return result;
}
static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
@@ -1314,10 +1351,10 @@
{0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
{0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
{0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
- {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
- {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
- {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
- {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp7x},
+ {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
+ {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
+ {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
+ {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
{0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
{0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
{0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
--
Developer quote of the year:
"We are juggling too many chainsaws and flaming arrows and tigers."
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