flashrom

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[commit] r961 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 16:15:36 2010 New Revision: 961 URL: http://flashrom.org/trac/coreboot/changeset/961 Log: unlock fixup Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/82802ab.c trunk/stm50flw0x0x.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Sat Mar 20 04:01:19 2010 (r960) +++ trunk/82802ab.c Sat Mar 20 16:15:36 2010 (r961) @@ -97,7 +97,7 @@ int i; //chipaddr wrprotect = flash->virtual_registers + page + 2; - for (i = 0; i < flash->total_size; i+= flash->page_size) + for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) { chip_writeb(0, flash->virtual_registers + i + 2); } Modified: trunk/stm50flw0x0x.c ============================================================================== --- trunk/stm50flw0x0x.c Sat Mar 20 04:01:19 2010 (r960) +++ trunk/stm50flw0x0x.c Sat Mar 20 16:15:36 2010 (r961) @@ -85,7 +85,7 @@ { int i; - for (i = 0; i < flash->total_size; i+= flash->page_size) { + for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) { if(unlock_block_stm50flw0x0x(flash, i)) { fprintf(stderr, "UNLOCK FAILED!\n"); return -1;

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[commit] r960 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 04:01:19 2010 New Revision: 960 URL: http://flashrom.org/trac/coreboot/changeset/960 Log: The Intel 28F001BX-T/B chips don't have block locks or mention of registers; chip is Old. The Intel 28F004S5 mentions block locks which require a remapping registers. Fixes problems brought up by carldani because of commit r948. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Mar 20 00:01:34 2010 (r959) +++ trunk/flashchips.c Sat Mar 20 04:01:19 2010 (r960) @@ -2316,7 +2316,6 @@ .model_id = P28F001BXB, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ - .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ @@ -2331,7 +2330,6 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, .write = NULL, .read = read_memmapped, }, @@ -2344,7 +2342,6 @@ .model_id = P28F001BXT, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ @@ -2359,7 +2356,6 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, .write = NULL, .read = read_memmapped, }, @@ -2372,6 +2368,7 @@ .model_id = E_28F004S5, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_REGISTERMAP, .tested = TEST_UNTESTED, .probe = probe_82802ab, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */

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MCP SPI dump
by Kevin Bosworth 20 Mar '10

20 Mar '10

Hi, I'm not sure if you really need this. But, here it is, the output from flashrom and lspci as mentioned on http://www.phoronix.com/forums/showthread.php?t=21054&highlight=flashrom. The attached info is for the motherboard Nvidia 790i Ultra SLI (part #-132-CK-NF79) by EVGA. Let me know if you need additional info. Thanks. Kevin

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[PATCH 06/11] Rebased Board Enable Patch: Asus P4B533-E Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
by Sean Nelson 20 Mar '10

20 Mar '10

--- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 89dad8a..13abc40 100644 --- a/board_enable.c +++ b/board_enable.c @@ -939,26 +939,27 @@ static int intel_ich_gpio19_raise(const char *name) * Suited for: * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ static int intel_ich_gpio21_raise(const char *name) { return intel_ich_gpio_set(21, 1); } /** * Suited for: * - Asus P4B266: socket478 + intel 845D + ICH2. + * - Asus P4B533-E: socket478 + 845E + ICH4 * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 */ static int intel_ich_gpio22_raise(const char *name) { return intel_ich_gpio_set(22, 1); } /** * Suited for HP Vectra VL400: 815 + ICH + PC87360. */ static int board_hp_vl400(const char *name) { -- 1.6.6

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[PATCH 11/11] Rebased Board Enable Patch: iBase MB899.
by Sean Nelson 20 Mar '10

20 Mar '10

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index b7b62f9..8692a98 100644 --- a/board_enable.c +++ b/board_enable.c @@ -974,26 +974,34 @@ static int board_hp_vl400(const char *name) } /** * Suited for: * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. */ static int intel_ich_gpio23_raise(const char *name) { return intel_ich_gpio_set(23, 1); } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) { int ret; /* Lower Blocks Lock -- pin 7 of PLCC32 */ ret = intel_ich_gpio_set(22, 1); if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ ret = intel_ich_gpio_set(23, 1); return ret; } @@ -1361,26 +1369,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, -- 1.6.6

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[commit] r959 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 00:01:34 2010 New Revision: 959 URL: http://flashrom.org/trac/coreboot/changeset/959 Log: Rebased Board Enable Patch: iBase MB899. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 20 00:00:07 2010 (r958) +++ trunk/board_enable.c Sat Mar 20 00:01:34 2010 (r959) @@ -984,6 +984,14 @@ } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) @@ -1371,6 +1379,7 @@ {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},

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[PATCH 10/11] Rebased Board Enable Patch: Abit AN-M2.
by Sean Nelson 20 Mar '10

20 Mar '10

Ah, right-o, pulled this out of my git repo where it has been sitting since the 24th :) Luc Verhaegen. --- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index de274e7..b7b62f9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1313,26 +1313,27 @@ static int it8712f_gpio3_1_raise(const char *name) * The coreboot ids are used two fold. When running with a coreboot firmware, * the ids uniquely matches the coreboot board identification string. When a * legacy bios is installed and when autodetection is not possible, these ids * can be used to identify the board through the -m command line argument. * * When a board is identified through its coreboot ids (in both cases), the * main pci ids are still required to match, as a safeguard. */ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, -- 1.6.6

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[commit] r958 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 00:00:07 2010 New Revision: 958 URL: http://flashrom.org/trac/coreboot/changeset/958 Log: Rebased Board Enable Patch: Abit AN-M2. Original patch by: Luc Verhaegen. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:58:15 2010 (r957) +++ trunk/board_enable.c Sat Mar 20 00:00:07 2010 (r958) @@ -1323,6 +1323,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},

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[PATCH 08/11] Reversed-engineered board enable for the ASUS A8N-LA. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L.
by Sean Nelson 19 Mar '10

19 Mar '10

Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> --- board_enable.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 731171c..aa9fec8 100644 --- a/board_enable.c +++ b/board_enable.c @@ -531,26 +531,27 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) base += 0xC0; tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) tmp |= 0x01; OUTB(tmp, base + gpio); return 0; } /** + * Suited for ASUS A8N-LA: nVidia MCP51. * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. */ static int nvidia_mcp_gpio0_raise(const char *name) { return nvidia_mcp_gpio_set(0x00, 1); } /** * Suited for Abit KN8 Ultra: nVidia CK804. */ static int nvidia_mcp_gpio2_lower(const char *name) { return nvidia_mcp_gpio_set(0x02, 0); @@ -1329,26 +1330,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, -- 1.6.6

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[commit] r957 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:58:15 2010 New Revision: 957 URL: http://flashrom.org/trac/coreboot/changeset/957 Log: Reversed-engineered board enable for the ASUS A8N-LA. Rebased. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L. This could match any HP Nagami board. Needs testing. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:55:48 2010 (r956) +++ trunk/board_enable.c Fri Mar 19 23:58:15 2010 (r957) @@ -541,6 +541,7 @@ } /** + * Suited for ASUS A8N-LA: nVidia MCP51. * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. */ static int nvidia_mcp_gpio0_raise(const char *name) @@ -1339,6 +1340,7 @@ {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},

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