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Re: [flashrom] [PATCH 2/3] Move SB600 SPI initialization to sb600spi.c
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

On 18.07.2010 16:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > chipset_enable.c | 79 ++--------------------------------------------------- > flash.h | 2 +- > sb600spi.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++- > 3 files changed, 80 insertions(+), 78 deletions(-) > > diff --git a/chipset_enable.c b/chipset_enable.c > index 7434d65..ad3b732 100644 > --- a/chipset_enable.c > +++ b/chipset_enable.c > @@ -683,10 +683,8 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) > > static int enable_flash_sb600(struct pci_dev *dev, const char *name) > { > - uint32_t tmp, prot; > + uint32_t prot; > uint8_t reg; > - struct pci_dev *smbus_dev; > - int has_spi = 1; > > /* Clear ROM protect 0-3. */ > for (reg = 0x50; reg < 0x60; reg += 4) { > @@ -710,80 +708,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) > (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); > } > > - /* Read SPI_BaseAddr */ > - tmp = pci_read_long(dev, 0xa0); > - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > - msg_pdbg("SPI base address is at 0x%x\n", tmp); > - > - /* If the BAR has address 0, it is unlikely SPI is used. */ > - if (!tmp) > - has_spi = 0; > - > - if (has_spi) { > - /* Physical memory has to be mapped at page (4k) boundaries. */ > - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > - 0x1000); > - /* The low bits of the SPI base address are used as offset into > - * the mapped page. > - */ > - sb600_spibar += tmp & 0xfff; > - > - tmp = pci_read_long(dev, 0xa0); > - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > - (tmp & 0x4) >> 2); > - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > - > - tmp = pci_read_byte(dev, 0xbb); > - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > - tmp & 0x1, (tmp & 0x20) >> 5); > - tmp = mmio_readl(sb600_spibar); > - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > - } > - > - /* Look for the SMBus device. */ > - smbus_dev = pci_dev_find(0x1002, 0x4385); > - > - if (has_spi && !smbus_dev) { > - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > - has_spi = 0; > - } > - if (has_spi) { > - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > - reg = pci_read_byte(smbus_dev, 0xAB); > - reg &= 0xC0; > - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > - if (reg != 0x00) > - has_spi = 0; > - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > - reg = pci_read_byte(smbus_dev, 0x83); > - reg &= 0xC0; > - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > - /* SPI_HOLD is not used on all boards, filter it out. */ > - if ((reg & 0x80) != 0x00) > - has_spi = 0; > - /* GPIO47/SPI_CLK status */ > - reg = pci_read_byte(smbus_dev, 0xA7); > - reg &= 0x40; > - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > - if (reg != 0x00) > - has_spi = 0; > - } > - > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; > - if (has_spi) { > - buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > - } > + > + sb600_probe_spi(dev); > sb600_spi_probe should return an error code which is checked. > > /* Read ROM strap override register. */ > OUTB(0x8f, 0xcd6); > diff --git a/flash.h b/flash.h > index a8ca6d7..8ebea29 100644 > --- a/flash.h > +++ b/flash.h > @@ -702,11 +702,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > +void sb600_probe_spi(struct pci_dev * dev); > space after * > int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > -extern uint8_t *sb600_spibar; > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > diff --git a/sb600spi.c b/sb600spi.c > index caf1a99..e42b20b 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -40,7 +40,82 @@ > *}; > */ > > -uint8_t *sb600_spibar = NULL; > +static uint8_t *sb600_spibar = NULL; > + > +void sb600_probe_spi(struct pci_dev * dev) > please make it return int, and kill the space after * > +{ > + struct pci_dev *smbus_dev; > + uint32_t tmp; > + uint8_t reg; > + /* Read SPI_BaseAddr */ > + tmp = pci_read_long(dev, 0xa0); > + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ > + msg_pdbg("SPI base address is at 0x%x\n", tmp); > + > + /* If the BAR has address 0, it is unlikely SPI is used. */ > + if (!tmp) > + return; > that would be return 0 > + > + /* Physical memory has to be mapped at page (4k) boundaries. */ > + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, > + 0x1000); > + /* The low bits of the SPI base address are used as offset into > + * the mapped page. > + */ > + sb600_spibar += tmp & 0xfff; > + > + tmp = pci_read_long(dev, 0xa0); > + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " > + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, > + (tmp & 0x4) >> 2); > + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; > + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); > + > + tmp = pci_read_byte(dev, 0xbb); > + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", > + tmp & 0x1, (tmp & 0x20) >> 5); > + tmp = mmio_readl(sb600_spibar); > + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " > + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " > + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", > + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, > + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, > + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); > + > + /* Look for the SMBus device. */ > + smbus_dev = pci_dev_find(0x1002, 0x4385); > + > + if (!smbus_dev) { > + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); > + return; > And this should be an error return. Do we want some define for ERROR_NONFATAL and make it some otherwise unusued value? Maybe 0x100 or something? > + } > + > + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ > + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ > + reg = pci_read_byte(smbus_dev, 0xAB); > + reg &= 0xC0; > + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); > + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); > + if (reg != 0x00) > + return; > Not an error, just a sign that SPI is not used. return 0; > + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ > + reg = pci_read_byte(smbus_dev, 0x83); > + reg &= 0xC0; > + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); > + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); > + /* SPI_HOLD is not used on all boards, filter it out. */ > + if ((reg & 0x80) != 0x00) > + return; > return 0; > + /* GPIO47/SPI_CLK status */ > + reg = pci_read_byte(smbus_dev, 0xA7); > + reg &= 0x40; > + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); > + if (reg != 0x00) > + return; > return 0; > + > + buses_supported |= CHIP_BUSTYPE_SPI; > + spi_controller = SPI_CONTROLLER_SB600; > +} > > int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Intel SE440BX
by Mattias Mattsson 22 Jul '10

22 Jul '10

Hi, I'm trying latest flashrom (r1082) an an Intel SE440BX. No flashchip is detected. I also tried to reuse the SE440BX-2 board enable but couldn't make it work. The flash on the board is an Intel E28F002BC-T80. Datasheet here: http://www.ezoflash.com/datasheets/flash/Intel/28F002BC.pdf I would like to add the chip to flashchips.c but was unsure how to interpret the datasheet and the corresponding values for probe/read/write function. Logs attached -mattias

4 5

[commit] r1097 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: hailfinger Date: Thu Jul 22 17:20:43 2010 New Revision: 1097 URL: http://flashrom.org/trac/coreboot/changeset/1097 Log: Add support for the Intel 28F002BC-T. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.c Thu Jul 22 17:20:43 2010 (r1097) @@ -2814,6 +2814,33 @@ { .vendor = "Intel", + .name = "28F002BC-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F002BC, + .total_size = 256, + .page_size = 256 * 1024, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "28F004S5", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jul 22 13:44:38 2010 (r1096) +++ trunk/flashchips.h Thu Jul 22 17:20:43 2010 (r1097) @@ -274,6 +274,7 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F002BC 0x7C /* 28F002BC-T */ #define P28F004BT 0x78 /* 28F004BV/BE-T */ #define P28F004BB 0x79 /* 28F004BV/BE-B */ #define P28F400BT 0x70 /* 28F400BV/CV/CE-T */

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[PATCH] Annotate evil twins
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

Evil twins are chips with identical IDs and different/incompatible characteristics (e.g. eraseblock layout, write strategy or size). Annotate them so flashrom can tell the user that it's not a matter of simply picking one of the chips in a list of multiple chips found. This patch only touches the AMIC A25L40PT and A25L40PU. I'm fairly sure there are more evil twins, but those two were touched recently. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-evil_twin/flash.h =================================================================== --- flashrom-evil_twin/flash.h (Revision 1096) +++ flashrom-evil_twin/flash.h (Arbeitskopie) @@ -180,6 +180,14 @@ #define FEATURE_ADDR_2AA (1 << 2) #define FEATURE_ADDR_AAA (2 << 2) #define FEATURE_ADDR_SHIFTED (1 << 5) +/* Evil twins are chips with the same ID and different erase/write + * characteristics. The second macro discards its arguments for now and allows + * human readable annotation while at the same time providing a zero cost + * simplified machine readable annotation. The first macro is there to check + * quickly if the chip has any evil twins. + */ +#define FEATURE_EVIL_TWIN (1 << 6) +#define FEATURE_EVIL_TWIN_OF(a,b) (1 << 6) struct flashchip { const char *vendor; Index: flashrom-evil_twin/flashchips.c =================================================================== --- flashrom-evil_twin/flashchips.c (Revision 1096) +++ flashrom-evil_twin/flashchips.c (Arbeitskopie) @@ -1372,6 +1372,7 @@ .model_id = AMIC_A25L40PT, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_EVIL_TWIN_OF("AMIC", "A25L40PU"), .tested = TEST_OK_PRW, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -1404,6 +1405,7 @@ .model_id = AMIC_A25L40PU, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_EVIL_TWIN_OF("AMIC", "A25L40PT"), .tested = TEST_OK_PRW, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, Index: flashrom-evil_twin/cli_classic.c =================================================================== --- flashrom-evil_twin/cli_classic.c (Revision 1096) +++ flashrom-evil_twin/cli_classic.c (Arbeitskopie) @@ -399,7 +399,8 @@ if (flashes[1]) { printf("Multiple flash chips were detected:"); for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + printf("%s %s%s", i ? "," : "", flashes[i]->name, + flashes[i]->feature_bits & FEATURE_EVIL_TWIN ? " (evil twin)" : ""); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); -- http://www.hailfinger.org/

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Output of "flashrom -V" for E Machines ET1300
by Brett Mahar 22 Jul '10

22 Jul '10

brett@local:~$ sudo flashrom -V flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "eMachines" DMI string system-product-name: "ET1300" DMI string system-version: "R01-A1" DMI string baseboard-manufacturer: "eMachines" DMI string baseboard-product-name: "EMCP61PM-GM" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8726 Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:03eb at 00:01:1 SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000 Mapping MCP67 SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x000a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 647M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. brett@local:~$

1 0

[RFC] Chip ID #defines
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

Parts of flashrom codebase are really old any nobody ever got around to cleaning them up. flashchips.h is one of those places with organic growth on top of historic cruft. Right now, most chip ID #defines have underscores somewhere in the first few characters of the name. For a sizable portion of flash chips this underscore does not make any sense if you look at the original chip name. My best guess is that someone originally thought that having a vendor name as part of the chip ID #define. For chips which have the vendor name as part of the chip name anyway this might make sense. A prominent example is SST_49LF080A. OTOH, stuff like W_25X10 is just really ugly. Besides that, grepping for those identifiers requires a lot of guesswork if you only know the chip name as printed on the chip. I am not sure if we really want to have underscores in random places in all those IDs. Nobody ever bothered to make those #defines look sane or consistent. Should we kill the underscore inside the chip name completely and instead use $VENDORNAME_$CHIPNAME for the #defines? IMHO that looks more natural and makes grepping easier. We'd still have to decide whether we should use the vendor name as it is used in $VENDOR_ID or a different form. For SST (and a few other manufacturers) this is not a problem because the vendor ID #define is SST_ID. However, for Winbond it gets a bit more difficult because we have WINBOND_ID and WINBOND_NEX_ID. W_25X10 would become either WINBOND_NEX_W25X10 or WINBOND_W25X10. I think the former variant makes it easier to visually cross-check if the vendor and chip ID combination makes sense. Sometimes multiple chips have the same ID. That's not a problem if the chips have identical characteristics and if they share one common entry in flashchips.c. We could add .alias_vendor and .alias_name fields (or any similar solution) to struct flashchip to accommodate chips where the vendor and chip name changed a few times in a way that can't be expressed easily with "oldname/newname". We also should definitely talk about evil twins. Those are chips with identical IDs but distinct/incompatible programming strategies. I sent a patch to mark some of them as evil twins, but we still have to decide if those evil twins should use the same #define for the ID or if they should use different #defines. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1096 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: hailfinger Date: Thu Jul 22 13:44:38 2010 New Revision: 1096 URL: http://flashrom.org/trac/coreboot/changeset/1096 Log: Add support for the following AMIC SPI chips: http://www.amictechnology.com/pdf/A25L20P.pdf covers: AMIC A25L05PT AMIC A25L05PU AMIC A25L10PT AMIC A25L10PU AMIC A25L20PT AMIC A25L20PU http://www.amictechnology.com/pdf/A25L16P.pdf covers: AMIC A25L16PT AMIC A25L16PU Clarify the situation surrounding the A25L40PT and A25L40PU chips which share the same RDID values, despite the fact that their erase block layouts are different. Rudolf Marek tested and confirmed the distinct erase block layouts of these chips. Add a pretty-printer for the AMIC SPI chip status register Add a generic AMIC chip type. Signed-off-by: Daniel Lenski <dlenski(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h trunk/spi25.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/flashchips.c Thu Jul 22 13:44:38 2010 (r1096) @@ -1169,14 +1169,207 @@ .read = read_memmapped, }, - /* The next two chip definitions have top/bottom boot blocks, but has no - device differentiation between the two */ + { + .vendor = "AMIC", + .name = "A25L05PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L05PT, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L05PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L05PU, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L10PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L10PT, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 1}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L10PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L10PU, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 1}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L20PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L20PT, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L20PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L20PU, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + /* The A25L40P{T,U} chips are distinguished by their + * erase block layouts, but without any distinction in RDID. + * This inexplicable quirk was verified by Rudolf Marek + * and discussed on the flashrom mailing list on 2010-07-12. + */ { .vendor = "AMIC", .name = "A25L40PT", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = AMIC_ID, - .model_id = AMIC_A25L40P, + .model_id = AMIC_A25L40PT, .total_size = 512, .page_size = 256, .tested = TEST_OK_PRW, @@ -1208,7 +1401,7 @@ .name = "A25L40PU", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = AMIC_ID, - .model_id = AMIC_A25L40P, + .model_id = AMIC_A25L40PU, .total_size = 512, .page_size = 256, .tested = TEST_OK_PRW, @@ -1269,6 +1462,76 @@ { .vendor = "AMIC", + .name = "A25L16PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L16PT, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 31}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L16PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L16PU, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PRW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 31}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", .name = "A29002B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, @@ -6678,6 +6941,21 @@ }, { + .vendor = "AMIC", + .name = "unknown AMIC SPI chip", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .write = NULL, + .read = NULL, + }, + + { .vendor = "Atmel", .name = "unknown Atmel SPI chip", .bustype = CHIP_BUSTYPE_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/flashchips.h Thu Jul 22 13:44:38 2010 (r1096) @@ -75,8 +75,19 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ -#define AMIC_A25L40P 0x2013 -#define AMIC_A25L80P 0x2014 +#define AMIC_A25L05PT 0x2020 +#define AMIC_A25L05PU 0x2010 +#define AMIC_A25L10PT 0x2021 +#define AMIC_A25L10PU 0x2011 +#define AMIC_A25L20PT 0x2022 +#define AMIC_A25L20PU 0x2012 +#define AMIC_A25L40PT 0x2013 /* Datasheet says T and U have + same device ID. Confirmed by + hardware testing. */ +#define AMIC_A25L40PU 0x2013 +#define AMIC_A25L80P 0x2014 /* Seems that no A25L80PT exists */ +#define AMIC_A25L16PT 0x2025 +#define AMIC_A25L16PU 0x2015 #define AMIC_A29002B 0x0d #define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/spi25.c Thu Jul 22 13:44:38 2010 (r1096) @@ -328,6 +328,16 @@ } /* Prettyprint the status register. Works for + * AMIC A25L series + */ +void spi_prettyprint_status_register_amic_a25l(uint8_t status) +{ + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_common(status); +} + +/* Prettyprint the status register. Works for * ST M25P series * MX MX25L series */ @@ -389,6 +399,10 @@ status = spi_read_status_register(); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { + case AMIC_ID: + if ((flash->model_id & 0xff00) == 0x2000) + spi_prettyprint_status_register_amic_a25l(status); + break; case ST_ID: if (((flash->model_id & 0xff00) == 0x2000) || ((flash->model_id & 0xff00) == 0x2500))

1 0

[PATCH] RayeR speedups, variable port
by Carl-Daniel Hailfinger 21 Jul '10

21 Jul '10

Speed up RayeR SPIPGM driver in flashrom by a factor of 2. Allow specification of an alternate base port with flashrom -p rayer_spi:lptport=0x278 Any port number is allowed as long as it is nonzero, below 65536 and a multiple of four. Untested, should work. Martin, this one should hopefully reach the speed of SPIPGM.exe for reads. I'll ask Idwer to provide a DOS binary for you. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_rayer_faster/flashrom.8 =================================================================== --- flashrom-bitbang_spi_rayer_faster/flashrom.8 (Revision 1093) +++ flashrom-bitbang_spi_rayer_faster/flashrom.8 (Arbeitskopie) @@ -394,7 +394,18 @@ (in Hz). The default is the maximum frequency of 8 MHz. .TP .BR "rayer_spi " programmer -No parameters defined yet. More information about the hardware is available at +The default I/O base address used for the parallel port is 0x378 and you can use +the optional +.B lptport +parameter to specify an alternate base I/O address with the +.sp +.B " flashrom \-p rayer_spi:lptport=portnum" +.sp +syntax where +.B portnum +is the I/O port number of your parallel port which must be a multiple of 4. +.sp +More information about the hardware is available at http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem Index: flashrom-bitbang_spi_rayer_faster/rayer_spi.c =================================================================== --- flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Revision 1093) +++ flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Arbeitskopie) @@ -30,6 +30,7 @@ */ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> #include "flash.h" /* We have two sets of pins, out and in. The numbers for both sets are @@ -42,7 +43,7 @@ /* Pins for slave->master direction */ #define SPI_MISO_PIN 6 -static int lpt_iobase; +static uint16_t lpt_iobase; /* FIXME: All rayer_bitbang_set_* functions could use caching of the value * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one @@ -50,37 +51,31 @@ * value. */ -void rayer_bitbang_set_cs(int val) +/* Cached value of last byte sent. */ +static uint8_t lpt_outval; + +static void rayer_bitbang_set_cs(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_CS_PIN); - tmp |= (val << SPI_CS_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_CS_PIN); + lpt_outval |= (val << SPI_CS_PIN); + OUTB(lpt_outval, lpt_iobase); } -void rayer_bitbang_set_sck(int val) +static void rayer_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_SCK_PIN); - tmp |= (val << SPI_SCK_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_SCK_PIN); + lpt_outval |= (val << SPI_SCK_PIN); + OUTB(lpt_outval, lpt_iobase); } -void rayer_bitbang_set_mosi(int val) +static void rayer_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_MOSI_PIN); - tmp |= (val << SPI_MOSI_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_MOSI_PIN); + lpt_outval |= (val << SPI_MOSI_PIN); + OUTB(lpt_outval, lpt_iobase); } -int rayer_bitbang_get_miso(void) +static int rayer_bitbang_get_miso(void) { uint8_t tmp; @@ -99,16 +94,49 @@ int rayer_spi_init(void) { - /* Pick a default value for now. */ - lpt_iobase = 0x378; + char *portpos = NULL; + /* Non-default port requested? */ + portpos = extract_programmer_param("lptport"); + if (portpos) { + char *endptr = NULL; + unsigned long tmp; + tmp = strtoul(portpos, &endptr, 0); + /* Port 0, port >0x1000, unaligned ports and garbage strings + * are rejected. + */ + if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) || + (*endptr != '\0')) { + /* Using ports below 0x100 is a really bad idea, and + * should only be done if no port between 0x100 and + * 0xfffc works due to routing issues. + */ + msg_perr("Error: lptport specified, but no valid " + "port specified.\nPort must be a multiple of " + "0x4 and lie between 0x100 and 0xfffc.\n"); + free(portpos); + return 1; + } else { + lpt_iobase = (uint16_t)tmp; + msg_pinfo("Non-default I/O base requested. This will " + "not change the hardware settings.\n"); + } + } else { + /* Pick a default value for the I/O base. */ + lpt_iobase = 0x378; + } + free(portpos); + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", lpt_iobase); get_io_perms(); - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + /* Get the initial value before writing to any line. */ + lpt_outval = INB(lpt_iobase); + + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; buses_supported = CHIP_BUSTYPE_SPI; -- http://www.hailfinger.org/

4 6

[commit] r1095 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 17:12:07 2010 New Revision: 1095 URL: http://flashrom.org/trac/coreboot/changeset/1095 Log: Add nicnatsemi to print.c and print_wiki.c. Change the nicnatsemi address mask to use MA0-MA16 and set the maximum decode size to 128KB. Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/nicnatsemi.c trunk/print.c trunk/print_wiki.c Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/nicnatsemi.c Wed Jul 21 17:12:07 2010 (r1095) @@ -43,6 +43,14 @@ buses_supported = CHIP_BUSTYPE_PARALLEL; + /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 + * in another. My NIC has MA16 connected to A16 on the boot ROM socket + * so I'm assuming it is accessible. If not then next line wants to be + * max_rom_decode.parallel = 65536; and the mask in the read/write + * functions below wants to be 0x0000FFFF. + */ + max_rom_decode.parallel = 131072; + return 0; } @@ -55,7 +63,7 @@ void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) { - OUTL((uint32_t)addr & 0x0000FFFF, io_base_addr + BOOT_ROM_ADDR); + OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. @@ -69,7 +77,7 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr) { - OUTL(((uint32_t)addr & 0x0000FFFF), io_base_addr + BOOT_ROM_ADDR); + OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/print.c Wed Jul 21 17:12:07 2010 (r1095) @@ -228,7 +228,7 @@ print_supported_boards_helper(boards_known, "boards"); print_supported_boards_helper(laptops_known, "laptops"); #endif -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #endif @@ -239,6 +239,9 @@ print_supported_pcidevs(nics_realtek); print_supported_pcidevs(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs(gfx_nvidia); #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/print_wiki.c Wed Jul 21 17:12:07 2010 (r1095) @@ -280,6 +280,9 @@ print_supported_pcidevs_wiki(nics_realtek); print_supported_pcidevs_wiki(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs_wiki(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs_wiki(gfx_nvidia); #endif

1 0

[RFC] National Semiconductor DP83815 NIC patch
by Andrew Morgan 21 Jul '10

21 Jul '10

Hi, I have a couple of Netgear FA311 network cards, which have DP83815DVNG chips on board, and a space to mount a 32-pin boot ROM socket. Looking at the datasheet for the chip I have created this patch. The datasheet suggests that reads and writes must be done 32 bits at a time, and only at 32 bit offsets. This seems strange for chips which have an 8 bit data bus. I don't think this code is ready for inclusion in flashrom yet, but if anyone has a card with this chip and can test it out then give it a go. I'm pretty sure it won't just work though. It might even destroy your computer/house/planet. I can't test it yet because the cards don't have a 32pin socket mounted on them. If and when I can add one then I can do some tests. This is my first 'large' patch so let me know what I have got wrong. :) Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> -- Andrew.

3 11

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