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[PATCH] Add SST25VF064C SPI flash
by Ed Swierk 21 Jul '10

21 Jul '10

Add definition for the SST25VF064C SPI flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/flashchips.c =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.c +++ flashrom-0.9.2-r1057/flashchips.c @@ -3871,6 +3871,40 @@ struct flashchip flashchips[] = { { .vendor = "SST", + .name = "SST25VF064C", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = SST_ID, + .model_id = SST_25VF064C, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .write = spi_chip_write_1, + .read = spi_chip_read, + }, + + { + .vendor = "SST", .name = "SST25VF040.REMS", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = SST_ID, Index: flashrom-0.9.2-r1057/flashchips.h =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.h +++ flashrom-0.9.2-r1057/flashchips.h @@ -399,6 +399,7 @@ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF064C 0x254B #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 #define SST_27SF512 0xA4

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[commit] r1094 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 17:02:22 2010 New Revision: 1094 URL: http://flashrom.org/trac/coreboot/changeset/1094 Log: Add support for the SST25VF064C SPI flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Jul 21 12:26:01 2010 (r1093) +++ trunk/flashchips.c Wed Jul 21 17:02:22 2010 (r1094) @@ -3971,6 +3971,41 @@ { .vendor = "SST", + .name = "SST25VF064C", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = SST_ID, + .model_id = SST_25VF064C, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, + .read = spi_chip_read, + }, + + { + .vendor = "SST", .name = "SST25VF040.REMS", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = SST_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Jul 21 12:26:01 2010 (r1093) +++ trunk/flashchips.h Wed Jul 21 17:02:22 2010 (r1094) @@ -400,6 +400,7 @@ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF064C 0x254B #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 #define SST_27SF512 0xA4

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[PATCH] Board enable for Dell OptiPlex GX1 400L+
by Mattias Mattsson 21 Jul '10

21 Jul '10

Board enable for Dell OptiPlex GX1 400L+ Logs and lspci output attached. Probe/Read/Write/Erase works. (After applying patch to add definition for 28F002BC/BL/BV/BX-T chip). Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: board_enable.c =================================================================== --- board_enable.c (revision 1093) +++ board_enable.c (working copy) @@ -1035,6 +1035,14 @@ } /** + * Suited for Dell OptiPlex GX1 400L+ + */ +static int intel_piix4_gpo30_lower(void) +{ + return intel_piix4_gpo_set(30, 0); +} + +/** * Set a GPIO line on a given Intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1679,6 +1687,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x1002, 0x4742, 0x1028, 0x0082, NULL, NULL, NULL, "Dell", "OptiPlex GX1 400L+", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},

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Re: [flashrom] [PATCH] Add support for RayeR SPIPGM hardware.
by Carl-Daniel Hailfinger 21 Jul '10

21 Jul '10

Hi, On 02.06.2010 09:47, RayeR wrote: > Carl-Daniel Hailfinger wrote: >> On 01.06.2010 11:54, rayer wrote: >>> it still hangs while autodetecting flash chip at AE49F2008 (is >>> displayed as last probed), >>> only with -c option it works. >>> >> Does it really work with -c CHIPNAME or do you need -f as well? >> > Yes, no -f needed. > Btw still problem with calibrating delay loop. The delay loop problem is now fixed. >> I found a bug in the bitbanging SPI core (buffer confusion) and fixed >> it. >> This version also reduces reach chunk size to 256 bytes instead of 65536 >> bytes. That makes buffer management more efficient (only one round of >> memory allocations). >> > I did't tested lpt-spi yet, I'll have to prepare some flash chip first... It would be cool if you could test the lpt-spi code. New flashrom.exe is available at http://khepri.openbios.org/~idwer/flashrom/r1039-patchwork-1441/ flashrom -p rayer_bitbang_spi -V Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1093 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 12:26:01 2010 New Revision: 1093 URL: http://flashrom.org/trac/coreboot/changeset/1093 Log: Add support for RayeR SPIPGM hardware as described in http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Martin Rehak <rayer(a)seznam.cz> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Added: trunk/rayer_spi.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/Makefile Wed Jul 21 12:26:01 2010 (r1093) @@ -111,8 +111,15 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes -# Bitbanging SPI infrastructure is not used yet. +# RayeR SPIPGM hardware support +CONFIG_RAYER_SPI ?= yes + +# Bitbanging SPI infrastructure, default off unless needed. +ifeq ($(CONFIG_RAYER_SPI), yes) +override CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -166,6 +173,13 @@ NEED_NET := yes endif +ifeq ($(CONFIG_RAYER_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_RAYER_SPI=1' +PROGRAMMER_OBJS += rayer_spi.o +# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct. +NEED_PCI := yes +endif + ifeq ($(CONFIG_BITBANG_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BITBANG_SPI=1' PROGRAMMER_OBJS += bitbang_spi.o Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flash.h Wed Jul 21 12:26:01 2010 (r1093) @@ -81,6 +81,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -129,6 +132,9 @@ enum bitbang_spi_master_type { BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ +#if CONFIG_RAYER_SPI == 1 + BITBANG_SPI_MASTER_RAYER, +#endif }; struct bitbang_spi_master { @@ -531,6 +537,11 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +/* rayer_spi.c */ +#if CONFIG_RAYER_SPI == 1 +int rayer_spi_init(void); +#endif + /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -650,6 +661,9 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + SPI_CONTROLLER_RAYER, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flashrom.8 Wed Jul 21 12:26:01 2010 (r1093) @@ -187,6 +187,9 @@ .sp .BR "* buspirate_spi" " (for SPI flash ROMs attached to a Bus Pirate)" .sp +.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport \ +based programmer)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -389,6 +392,10 @@ can be any of .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M ", " 8M (in Hz). The default is the maximum frequency of 8 MHz. +.TP +.BR "rayer_spi " programmer +No parameters defined yet. More information about the hardware is available at +http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. @@ -411,6 +418,9 @@ .BR gfxnvidia " and " drkaiser need PCI configuration space access and raw memory access. .sp +.B rayer_spi +needs raw I/O port access. +.sp .B satasii needs PCI configuration space read access and raw memory access. .sp Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flashrom.c Wed Jul 21 12:26:01 2010 (r1093) @@ -48,7 +48,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -86,6 +86,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI +#endif ; #endif @@ -380,6 +383,25 @@ .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + +#if CONFIG_RAYER_SPI == 1 + { + .name = "rayer_spi", + .init = rayer_spi_init, + .shutdown = noop_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, Added: trunk/rayer_spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/rayer_spi.c Wed Jul 21 12:26:01 2010 (r1093) @@ -0,0 +1,122 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak. + * See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions. + */ + +/* This driver uses non-portable direct I/O port accesses which won't work on + * any non-x86 platform, and even on x86 there is a high chance there will be + * collisions with any loaded parallel port drivers. + * The big advantage of direct port I/O is OS independence and speed because + * most OS parport drivers will perform many unnecessary accesses although + * this driver just treats the parallel port as a GPIO set. + */ +#if defined(__i386__) || defined(__x86_64__) + +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ +/* Pins for master->slave direction */ +#define SPI_CS_PIN 5 +#define SPI_SCK_PIN 6 +#define SPI_MOSI_PIN 7 +/* Pins for slave->master direction */ +#define SPI_MISO_PIN 6 + +static int lpt_iobase; + +/* FIXME: All rayer_bitbang_set_* functions could use caching of the value + * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one + * INB(lpt_iobase) would be needed on programmer init to get the initial + * value. + */ + +void rayer_bitbang_set_cs(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_CS_PIN); + tmp |= (val << SPI_CS_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_sck(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_SCK_PIN); + tmp |= (val << SPI_SCK_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_mosi(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_MOSI_PIN); + tmp |= (val << SPI_MOSI_PIN); + OUTB(tmp, lpt_iobase); +} + +int rayer_bitbang_get_miso(void) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase + 1); + tmp = (tmp >> SPI_MISO_PIN) & 0x1; + return tmp; +} + +static const struct bitbang_spi_master bitbang_spi_master_rayer = { + .type = BITBANG_SPI_MASTER_RAYER, + .set_cs = rayer_bitbang_set_cs, + .set_sck = rayer_bitbang_set_sck, + .set_mosi = rayer_bitbang_set_mosi, + .get_miso = rayer_bitbang_get_miso, +}; + +int rayer_spi_init(void) +{ + /* Pick a default value for now. */ + lpt_iobase = 0x378; + + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", + lpt_iobase); + + get_io_perms(); + + /* 1 usec halfperiod delay for now. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + return 1; + + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_RAYER; + + return 0; +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/spi.c Wed Jul 21 12:26:01 2010 (r1093) @@ -121,6 +121,15 @@ }, #endif +#if CONFIG_RAYER_SPI == 1 + { /* SPI_CONTROLLER_RAYER */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, +#endif + {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ };

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[PATCH] Intel chip id fix-up
by Mattias Mattsson 21 Jul '10

21 Jul '10

Strip package prefix in constant names (everything before "28F"). Prefix every constant name with I_ as in "Intel". Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> I_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> I_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> I_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> I_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> I_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> I_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> I_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> I_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> I_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BC/BL/BV/BX-T 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1092) +++ flashchips.c (working copy) @@ -2499,10 +2499,10 @@ { .vendor = "Intel", - .name = "28F001BX-B", + .name = "28F001BN/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXB, + .model_id = I_28F001B, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ .tested = TEST_UNTESTED, @@ -2525,10 +2525,10 @@ { .vendor = "Intel", - .name = "28F001BX-T", + .name = "28F001BN/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXT, + .model_id = I_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ .tested = TEST_UNTESTED, @@ -2551,10 +2551,10 @@ { .vendor = "Intel", - .name = "28F004S5", + .name = "28F008S3/S5/SC", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = E_28F004S5, + .model_id = I_28F004S3, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, @@ -2574,10 +2574,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-B", + .name = "28F004B5/BE/BV/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BB, + .model_id = I_28F004B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -2601,10 +2601,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-T", + .name = "28F004B5/BE/BV/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BT, + .model_id = I_28F004T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -2628,10 +2628,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-B", + .name = "28F400BV/BX/CE/CV-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BB, + .model_id = I_28F400B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, @@ -2656,10 +2656,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-T", + .name = "28F400BV/BX/CE/CV-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BT, + .model_id = I_28F400T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, Index: flashchips.h =================================================================== --- flashchips.h (revision 1092) +++ flashchips.h (working copy) @@ -256,17 +256,45 @@ #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ +#define I_28F320J5 0x14 +#define I_28F640J5 0x15 +#define I_28F320J3 0x16 +#define I_28F640J3 0x17 +#define I_28F128J3 0x18 +#define I_28F256J3 0x1D +#define I_28F400T 0x70 /* 28F400BV/BX/CE/CV-T */ +#define I_28F400B 0x71 /* 28F400BV/BX/CE/CV-B */ +#define I_28F200T 0x74 /* 28F200BL/BV/BX/CV-T */ +#define I_28F200B 0x75 /* 28F200BL/BV/BX/CV-B */ +#define I_28F004T 0x78 /* 28F004B5/BE/BV/BX-T */ +#define I_28F004B 0x79 /* 28F004B5/BE/BV/BX-B */ +#define I_28F002T 0x7C /* 28F002BC/BL/BV/BX-T */ +#define I_28F002B 0x7D /* 28F002BL/BV/BX-B */ +#define I_28F001T 0x94 /* 28F001BN/BX-T */ +#define I_28F001B 0x95 /* 28F001BN/BX-B */ +#define I_28F008T 0x98 /* 28F008BE/BV-T */ +#define I_28F008B 0x99 /* 28F008BE/BV-B */ +#define I_28F800T 0x9C /* 28F800B5/BV/CE/CV-T */ +#define I_28F800B 0x9D /* 28F800B5/BV/CE/CV-B */ +#define I_28F016SV 0xA0 /* 28F016SA/SV */ +#define I_28F008SA 0xA2 +#define I_28F008S3 0xA6 /* 28F008S3/S5/SC */ +#define I_28F004S3 0xA7 /* 28F008S3/S5/SC */ +#define I_28F016XS 0xA8 +#define I_28F016S3 0xAA /* 28F016S3/S5/SC */ +#define I_82802AC 0xAC #define I_82802AB 0xAD -#define I_82802AC 0xAC -#define E_28F004S5 0xA7 -#define E_28F008S5 0xA6 -#define E_28F016S5 0xAA -#define P28F001BXT 0x94 /* 28F001BX-T */ -#define P28F001BXB 0x95 /* 28F001BX-B */ -#define P28F004BT 0x78 /* 28F004BV/BE-T */ -#define P28F004BB 0x79 /* 28F004BV/BE-B */ -#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ -#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ +#define I_28F010 0xB4 +#define I_28F512 0xB8 +#define I_28F256A 0xB9 +#define I_28F020 0xBD +#define I_28F016B3T 0xD0 /* 28F016B3-T */ +#define I_28F016B3B 0xD1 /* 28F016B3-B */ +#define I_28F008B3T 0xD2 /* 28F008B3-T */ +#define I_28F008B3B 0xD3 /* 28F008B3-B */ +#define I_28F004B3T 0xD4 /* 28F004B3-T */ +#define I_28F004B3B 0xD5 /* 28F004B3-B */ + #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */

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Problem with FLASHROM, results in error while updating BIOS. Please help me urgently..
by Ajay Pai P: 21 Jul '10

21 Jul '10

Dear Sir, I had troubles in booting my system (ASUS A8N-Vm motherboard with AMI BIOS) ie. it would boot only every alternate times. So the first time I boot it, the motherboard seems to run fine (with all the necessary lights on and the cpu fan running) however there is no output on my monitor and the monitor power led simply keeps blinking. All I have to do is shut it down once by pressing the Power off/on button for long and then again switch on after which it boots simply fine. It doesnt seem to be because of cold start because even if i switch off my system after keeping it on for a long time, and try to boot it immediately, I have to again follow this procedure.I got my monitor tested and its fine. So i doubt my BIOS now. I tried updating it with Flashrom as follows and it results in error: $ sudo flashrom -w /media/BACKUP/Backups/OS\ backups/windows/A8N-VM-ASUS-0902.ROM flashrom v0.9.2-r1001 on Linux 2.6.31-ARCH (x86_64), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease) flashrom is free software, get the source code at http://www.flashrom.org No coreboot table found. Found chipset "NVIDIA MCP51", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000008! Expected=0xff, Read=0x90, failed byte count from 0x00000000-0x00000fff: 0xfe7 ERASE FAILED! ERASE FAILED at 0x00000008! Expected=0xff, Read=0x90, failed byte count from 0x00000000-0x0000ffff: 0xfefe ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Now I am not able to decide what is to be done. I am not sure if I ran the commands properly or if the BIOS chip is fine or not. I hereby request you to please guide me and help me overcome this problem and get my PC running fine. I shall be looking forward to your reply with crossed fingers. Thanking you in advance. -- Regards.... Ajay Pai P

2 1

Flashrom output
by Marco Schröder 21 Jul '10

21 Jul '10

Hello Gys, I`m so sorry but my english ist not perfect. I will send the output of flashrom -V for my Bios. Chipset: MCP61 Manufakter: ECS GeForce6100SM-M2 On the external Part of this email i have included two PDF: once of the Motherboard and once of the flashrom output. Thanks Best regards -- Two non-text attachments have been stripped from this message: GeForce6100SM-M2_V1.0A.pdf flashrom-output.pdf

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Re: [flashrom] [coreboot] SPI in-system programming
by Carl-Daniel Hailfinger 19 Jul '10

19 Jul '10

Hi Corey, [adding flashrom(a)flashrom.org to CC] On 18.07.2010 11:54, Corey Osgood wrote: > I need a way that I can test images without actually being in the same > location as the board I'll be testing them on. What would you guys > recommend for programming an SPI chip with it still on the > motherboard? flashrom. > There is no ISP header, and the flash chip is socketed, > the board will be a Zotac Atom/NM10 ITX board. You could stack two SPI chips easily, and switch the CS# pin. > I've seen programmers > that explain how to isolate the signals so their programmer can be > used to do it, but does it require a special programmer, or is it > something that could be done with a $20 ebay programmer and a little > wire? And can the board be operated with the programmer still > attached? I'm getting a lot of conflicting info, hoping someone can > clarify this. > If you want to reflash with an external programmer, it gets complicated really fast. Reflashing a chip which is connected to a running system is extremely risky, and you may fry your board. One way around that is to hook some buffer in between, but you'd need one which is fast enough for 33 MHz operation (and you want a safety margin to not disturb communication, so shooting for one with a delay around 10 ns is a good idea), and then electrically disconnect the flash chip from the board while flashing. Maybe flashing a chip in a powered down system with an external programmer works, but you can't be sure if the external programmer has enough power to feed 3.3V to the whole board (if the flash chip is connected there) and you may see undesirable side effects as well. > If this doesn't work out, how can I flip back and forth between a pair > of SPI chips? > Switching the CS# pin should do the trick. Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom on iMac4,1
by Mattias Mattsson 19 Jul '10

19 Jul '10

Hi, I ran latest flashrom (r1092) on an Intel iMac4,1. Probe, read, verify works. Write/Erase fails (nothing is erased or written). Logs attached. -mattias

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