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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Thu, 14 Aug 2014 11:52:21 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > (implicit question: is there a parameter to set SPI > frequency for the internal programmer?) Not for the Intel chipsets. But we use the lowest available frequency anyway (20 MHz), so it would probably not help you anyway. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Carl-Daniel Hailfinger 14 Aug '14

14 Aug '14

Hi Ricardo, your log is weird in a way I've never seen before. Details below. Am 13.08.2014 21:24 schrieb Ricardo Menzer: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. > > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805 > > > 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: >> > Hi guys! >> > I'm working with this COM Express module from Adlink >> > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) >> > and sometimes it doesn't recognize it's flash chip. >> > The following log happened after a failed probing. I then let the >> > board resting some time and tried to program again, with the results >> > bellow. >> > >> > This is a quite problematic module. Frequently it fails to probe the >> > flash chip. I have to reboot the system so it can see it again. It >> > also seems to corrupt the module flash even if I select to write to >> > the baseboard flash. I don't know if it's a flashrom issue or a >> > bios/hardware issue. >> > >> > I can safely reboot the system because we have a second flash on the baseboard. >> > >> > Right now I am using the module's flash to play with coreboot and i'm >> > maintaining a copy of the original BIOS on the baseboard. Changing the >> > role of both chips doesn't seem to change much, except for the >> > corruption issue (didn't made much tests yet, though). >> > >> > I have a Kontron module that I use in this same base board and it >> > works pretty well. >> > >> > >> > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address >> > 0xffe00000. >> > Reading old flash chip contents... done. >> > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 >> > spi_block_erase_20 failed during command execution at address 0x0 >> > Reading current flash chip contents... Error: SCIP never cleared! >> > Can't read anymore! Aborting. >> > FAILED! >> > Uh oh. Erase/write failed. Checking if anything changed. >> > Error: SCIP never cleared! >> > Your flash chip is in an unknown state. >> > Get help on IRC at chat.freenode.net (channel #flashrom) or >> > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! >> > ------------------------------------------------------------------------------- >> > DO NOT REBOOT OR POWEROFF! >> > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w >> > /media/sda1/coreboot.rom >> > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) >> > flashrom is free software, get the source code at http://www.flashrom.org >> > >> > Calibrating delay loop... OK. >> > sh: dmidecode: command not found >> > dmidecode execution unsuccessful - continuing without DMI info >> > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. >> > Please supply the board vendor and model name with the -p >> > internal:mainboard=<vendor>:<model> option. >> > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. >> > Error: SCIP never cleared! >> > Error: SCIP never cleared! > > flash1.log > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.2.0, GCC 4.8.2, little endian > Command line (3 args): /home/root/flashrom-0.9.7/flashrom -p internal -V > Calibrating delay loop... OS timer resolution is 4 usecs, 292M loops per second, 10 myus = 13 us, 100 myus = 101 us, 1000 myus = 1016 us, 10000 myus = 10057 us, 16 myus = 19 us, OK. > Initializing internal programmer > No coreboot table found. > Found Winbond Super I/O, id 0x52 > Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek" with PCI ID 8086:8186. Enabling flash write... > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > BIOS Prefetch Enable: disabled, > Root Complex Register Block address = 0xfed1c000 > SPIBAR = 0xfed1c000 + 0x3020 > 0x00: 0x0004 (SPIS) > 0x02: 0x41c0 (SPIC) > 0x04: 0x00000000 (SPIA) > 0x08: 0x41414125 (SPID0) > 0x0c: 0x00000000 (SPID0+4) > 0x10: 0x00000000 (SPID1) > 0x14: 0x00000000 (SPID1+4) > 0x18: 0x00000000 (SPID2) > 0x1c: 0x00000000 (SPID2+4) > 0x20: 0x00000000 (SPID3) > 0x24: 0x00000000 (SPID3+4) > 0x28: 0x00000000 (SPID4) > 0x2c: 0x00000000 (SPID4+4) > 0x30: 0x00000000 (SPID5) > 0x34: 0x00000000 (SPID5+4) > 0x38: 0x00000000 (SPID6) > 0x3c: 0x00000000 (SPID6+4) > 0x40: 0x00000000 (SPID7) > 0x44: 0x00000000 (SPID7+4) > 0x50: 0x00000000 (BBAR) > 0x54: 0x5006 (PREOP) > 0x56: 0x063b (OPTYPE) > 0x58: 0x05200302 (OPMENU) > 0x5c: 0x0050019f (OPMENU+4) > 0x60: 0x00000000 (PBR0) > 0x64: 0x00000000 (PBR1) > 0x68: 0x00000000 (PBR2) > Programming OPCODES... done > SPI Read Configuration: prefetching disabled, caching enabled, OK. > The following protocols are supported: Parallel, LPC, FWH, SPI. > Probing for AMIC A25L05PT, 64 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L10PU, 128 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L40PT, 512 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L16PT, 2048 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 > Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xbf, id2 0x2541 > Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x25, id2 0x41bf > Probing for AMIC A25L020, 256 kB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x41, id2 0xbf25 As you can see, the chip continuously outputs 0xbf 0x25 0x41 in an endless loop. Normally, the SST SST25VF016B chip should always return the same ID response to probe_spi_rdid_generic: id1 0xbf, id2 0x2541. However, your chip seems to be cycling through shifted variants of that response. This indicates the chip never leaves ID (read JEDEC ID with command 0x9f) mode, probably because the CE# (chip enable) line is stuck on low. I've never seen that happen before, and it's certainly really weird. Do you have a multimeter to confirm that the CE# pin of the flash chip is indeed continuously at 0V? The Intel Tunnel Creek chipset may be at fault, or some other weird component is screwing things up. Two things I'd like you to try: - Compile latest flashrom from source, reboot and then write a log file with the new flashrom using -o logfile.txt . It needs to be the first run after the reboot or we'll get mostly random results. - Put an oscilloscope on the CE# line and check if it ever goes to high (3.3V) again after a flashrom run. Regards, Carl-Daniel

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Stefan Tauner 14 Aug '14

14 Aug '14

On Wed, 13 Aug 2014 16:24:43 -0300 Ricardo Menzer <ricardomenzer(a)gmail.com> wrote: > I have also found that if I probe the chip three times, it will work > only once. I mean, if I probe for the chip and it is found, the next > two probes will fail. The third will work, and the next two will fail > again, and so on. > I'm attaching the logs for three consecutive probes and also the > output of lspci -vvxxxnn. Hi, the logs look really weird. Is it possible that the boot* SPI bus is shared with something else? The block diagram in the datasheet does not look very detailed. *IIRC that SoC has more than one SPI master. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Chips requiring 12 volts on VPP for erase and write
by Daniele Forsi 14 Aug '14

14 Aug '14

Hello, I have an Intel P28F001 flash memory which flashrom knows as INTEL_28F001T and lists with .tested = TEST_OK_PR I can confirm that reading works with -p internal but erasing and writing don't work because according to its datasheet it needs 12 volts on VPP (min 11.4 max 12.6) should this fact about 12V VPP recorded somewhere? the same for the B variant (which I haven't got) -- Daniele Forsi

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Re: [flashrom] FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

I have also found that if I probe the chip three times, it will work only once. I mean, if I probe for the chip and it is found, the next two probes will fail. The third will work, and the next two will fail again, and so on. I'm attaching the logs for three consecutive probes and also the output of lspci -vvxxxnn. Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805 2014-08-13 12:15 GMT-03:00 Ricardo Menzer <ricardomenzer(a)gmail.com>: > Hi guys! > I'm working with this COM Express module from Adlink > (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) > and sometimes it doesn't recognize it's flash chip. > The following log happened after a failed probing. I then let the > board resting some time and tried to program again, with the results > bellow. > > This is a quite problematic module. Frequently it fails to probe the > flash chip. I have to reboot the system so it can see it again. It > also seems to corrupt the module flash even if I select to write to > the baseboard flash. I don't know if it's a flashrom issue or a > bios/hardware issue. > > I can safely reboot the system because we have a second flash on the baseboard. > > Right now I am using the module's flash to play with coreboot and i'm > maintaining a copy of the original BIOS on the baseboard. Changing the > role of both chips doesn't seem to change much, except for the > corruption issue (didn't made much tests yet, though). > > I have a Kontron module that I use in this same base board and it > works pretty well. > > > 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address > 0xffe00000. > Reading old flash chip contents... done. > Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 > spi_block_erase_20 failed during command execution at address 0x0 > Reading current flash chip contents... Error: SCIP never cleared! > Can't read anymore! Aborting. > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Error: SCIP never cleared! > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! > ------------------------------------------------------------------------------- > DO NOT REBOOT OR POWEROFF! > 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w > /media/sda1/coreboot.rom > flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. > Please supply the board vendor and model name with the -p > internal:mainboard=<vendor>:<model> option. > Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > Error: SCIP never cleared! > ^C > 14:58:09 root ~ # > > > Ricardo Menzer > ricardomenzer(a)gmail.com > (32)8865-8805

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FAILED: Adlink NanoX-TC
by Ricardo Menzer 13 Aug '14

13 Aug '14

Hi guys! I'm working with this COM Express module from Adlink (http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1001&seq=&id=&sid…) and sometimes it doesn't recognize it's flash chip. The following log happened after a failed probing. I then let the board resting some time and tried to program again, with the results bellow. This is a quite problematic module. Frequently it fails to probe the flash chip. I have to reboot the system so it can see it again. It also seems to corrupt the module flash even if I select to write to the baseboard flash. I don't know if it's a flashrom issue or a bios/hardware issue. I can safely reboot the system because we have a second flash on the baseboard. Right now I am using the module's flash to play with coreboot and i'm maintaining a copy of the original BIOS on the baseboard. Changing the role of both chips doesn't seem to change much, except for the corruption issue (didn't made much tests yet, though). I have a Kontron module that I use in this same base board and it works pretty well. 14:55:12 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Found SST flash chip "SST25VF016B" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... timeout, ICH7_REG_SPIS=0x0001 spi_block_erase_20 failed during command execution at address 0x0 Reading current flash chip contents... Error: SCIP never cleared! Can't read anymore! Aborting. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Error: SCIP never cleared! Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! 14:56:28 root ~ # flashrom-0.9.7/flashrom -p internal -w /media/sda1/coreboot.rom flashrom v0.9.7-r1711 on Linux 3.10.38-ltsi-yocto-standard (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Warning: Can't autodetect MSC Q7-TCTC, DMI info unavailable. Please supply the board vendor and model name with the -p internal:mainboard=<vendor>:<model> option. Found chipset "Intel Atom E6xx(T)/Tunnel Creek". Enabling flash write... OK. Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! Error: SCIP never cleared! ^C 14:58:09 root ~ # Ricardo Menzer ricardomenzer(a)gmail.com (32)8865-8805

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 13 Aug '14

13 Aug '14

One other additional thought regarding partial read/write: the current logic all will fail to erase&write all-zero newcontent. Instead, if the reader bails (read_all_first == 0), the copy_old_content() logic should still read old included regions. In other words, it should do the opposite of what it currently does. +Reardon On Tue, Aug 12, 2014 at 8:53 PM, TR Reardon <thomas_reardon(a)hotmail.com> wrote: > Ok, sorry for my misunderstanding. But even with that change, > copy_old_content() still gets called to copy the old non-readable > regions. Shouldn't copy_old_content() just set oldcontent and > newcontent to all-ones for excluded regions? > > The unselected regions are not automatically skipped by the "do I need > to erase and then update this block?" comparison logic in > need_erase(), correct? At least, when I run it, the excluded regions > are erased (rather than skipped), but then not written. > > Anyway, I made one minor adjustment to your layout patches for partial > read, else segfault: > > --- > diff --git a/flashrom.c b/flashrom.c > index 27d1736..e3639ae 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1286,10 +1286,10 @@ int write_image_to_file(const unsigned char > *buf, unsigned long size, const char > l = get_next_included_romentry(0); > > while (l != NULL) { > - const char* name = (l->file[0] == '\0') ? l->name : l->file; > + const char* name = (l->file == NULL || l->file[0] == > '\0') ? l->name : l->file; > unsigned int len = l->end - l->start + 1; > msg_gdbg2("Writing \"%s\" to \"%s\" 0x%08x - 0x%08x (%uB)... ", > - l->name, l->file, l->start, l->end, len); > + l->name, name, l->start, l->end, len); > if (write_buf_to_file(buf + l->start, len, name) != 0) { > msg_gdbg2("failed.\n"); > return 1; > +Reardon > > > On Tue, Aug 12, 2014 at 4:33 PM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at> wrote: >> On Mon, 11 Aug 2014 19:14:53 -0400 >> TR Reardon <thomas_reardon(a)hotmail.com> wrote: >> >>> I'd like to start experimenting with partial-write support, now that >>> partial-read works well for me. But as of now doit() does a full read >>> before the write, which of course fails. Any updates that I could test? >>> Any useful log I can provide regarding successes? >>> >>> Note, I now have a buspirate so I can do full writes to recover, as needed >>> (this works successfully now, if slowly) >> >> As I wrote in my previous mail, (after applying the layout patches) you >> can disable the full read in doit() by setting read_all_first to 0. >> There are no further changes yet, because it does not make much sense >> until the proposed ones are merged... >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >>

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Re: [flashrom] flashrom Rangeley with WINDBOND25Q64
by Stefan Tauner 13 Aug '14

13 Aug '14

On Tue, 12 Aug 2014 15:54:20 -0600 Rich Futyma <rich.futyma(a)sanmina.com> wrote: > In addition to what Stefan described about ME descriptors, there is also > BIOS CNTL register, that if BIOS > enables it, you will not be able to write to flash using flashrom. Hello Rich, the above is true, but not relevant in this case, since the locking is disabled and writing enabled (according to the flashrom log). > CONFIDENTIALITY > This e-mail message and any attachments thereto, is intended only for use by the addressee(s) named herein and may contain legally privileged and/or confidential information. If you are not the intended recipient of this e-mail message, you are hereby notified that any dissemination, distribution or copying of this e-mail message, and any attachments thereto, is strictly prohibited. If you have received this e-mail message in error, please immediately notify the sender and permanently delete the original and any copies of this email and any prints thereof. > ABSENT AN EXPRESS STATEMENT TO THE CONTRARY HEREINABOVE, THIS E-MAIL IS NOT INTENDED AS A SUBSTITUTE FOR A WRITING. Notwithstanding the Uniform Electronic Transactions Act or the applicability of any other law of similar substance and effect, absent an express statement to the contrary hereinabove, this e-mail message its contents, and any attachments hereto are not intended to represent an offer or acceptance to enter into a contract and are not otherwise intended to bind the sender, Sanmina Corporation (or any of its subsidiaries), or any other person or entity. > You will be ridiculed sooner or later for using such a signature on public mailing lists ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Avoton patches for flashrom
by TR Reardon 13 Aug '14

13 Aug '14

Attempted write failed. Log attached. Haven't looked at further, but seems like partial reads work, but partial writes fail, due to early full-read before attempted partial-write. I use the term "partial" to mean a single region in the layout file. +Reardon

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Re: [flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.
by Marc Jones 13 Aug '14

13 Aug '14

On Fri, Aug 1, 2014 at 6:39 PM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Possible values as well as encodings have changed in newer chipsets as follows. > - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all > operations > - Since Cougar Point the chipsets support dual output fast reads (encoded > in bit 30). > - Flash component density encoding has changed from 3 to 4 bits with Lynx > Point, currently allowing for up to 64 MB chips. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > ich_descriptors.c | 182 +++++++++++++++++------ > ich_descriptors.h | 39 ++++- > ichspi.c | 24 ++- > util/ich_descriptors_tool/ich_descriptors_tool.c | 4 + > 4 files changed, 193 insertions(+), 56 deletions(-) > > diff --git a/ich_descriptors.c b/ich_descriptors.c > index 528717b..3977a4b 100644 > --- a/ich_descriptors.c > +++ b/ich_descriptors.c > @@ -64,7 +64,7 @@ void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) > void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) > { > prettyprint_ich_descriptor_content(&desc->content); > - prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_component(cs, desc); > prettyprint_ich_descriptor_region(desc); > prettyprint_ich_descriptor_master(&desc->master); > #ifdef ICH_DESCRIPTORS_FROM_DUMP > @@ -98,28 +98,97 @@ void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) > msg_pdbg2("\n"); > } > > -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) > +static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) > +{ > + if (idx > 1) { > + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > + return NULL; > + } > + > + if (desc->content.NC == 0 && idx > 0) > + return "unused"; > + > + static const char * const size_str[] = { > + "512 kB", /* 0000 */ > + "1 MB", /* 0001 */ > + "2 MB", /* 0010 */ > + "4 MB", /* 0011 */ > + "8 MB", /* 0100 */ > + "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */ > + "32 MB", /* 0110 */ > + "64 MB", /* 0111 */ > + }; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: { > + uint8_t size_enc; > + if (idx == 0) { > + size_enc = desc->component.old.comp1_density; > + } else { > + size_enc = desc->component.old.comp2_density; > + } > + if (size_enc > 5) > + return "reserved"; > + return size_str[size_enc]; > + } > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: { > + uint8_t size_enc; > + if (idx == 0) { > + size_enc = desc->component.new.comp1_density; > + } else { > + size_enc = desc->component.new.comp2_density; > + } > + if (size_enc > 7) > + return "reserved"; > + return size_str[size_enc]; > + } > + case CHIPSET_ICH_UNKNOWN: > + default: > + return "unknown"; > + } > +} > + > +static const char *pprint_freq(enum ich_chipset cs, uint8_t value) > { > static const char * const freq_str[8] = { > "20 MHz", /* 000 */ > "33 MHz", /* 001 */ > "reserved", /* 010 */ > "reserved", /* 011 */ > - "50 MHz", /* 100 */ > + "50 MHz", /* 100 */ /* New since Ibex Peak */ > "reserved", /* 101 */ > "reserved", /* 110 */ > "reserved" /* 111 */ > }; > - static const char * const size_str[8] = { > - "512 kB", /* 000 */ > - " 1 MB", /* 001 */ > - " 2 MB", /* 010 */ > - " 4 MB", /* 011 */ > - " 8 MB", /* 100 */ > - " 16 MB", /* 101 */ > - "reserved", /* 110 */ > - "reserved", /* 111 */ > - }; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + if (value > 1) > + return "reserved"; > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: > + return freq_str[value]; > + case CHIPSET_ICH_UNKNOWN: > + default: > + return "unknown"; > + } > +} > + > +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) > +{ > > msg_pdbg2("=== Component Section ===\n"); > msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); > @@ -127,24 +196,21 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) > msg_pdbg2("\n"); > > msg_pdbg2("--- Details ---\n"); > - msg_pdbg2("Component 1 density: %s\n", > - size_str[desc->component.comp1_density]); > + msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0)); > if (desc->content.NC) > - msg_pdbg2("Component 2 density: %s\n", > - size_str[desc->component.comp2_density]); > + msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); > else > msg_pdbg2("Component 2 is not used.\n"); > - msg_pdbg2("Read Clock Frequency: %s\n", > - freq_str[desc->component.freq_read]); > - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > - freq_str[desc->component.freq_read_id]); > - msg_pdbg2("Write and Erase Clock Freq.: %s\n", > - freq_str[desc->component.freq_write]); > - msg_pdbg2("Fast Read is %ssupported.\n", > - desc->component.fastread ? "" : "not "); > - if (desc->component.fastread) > + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); > + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); > + if (desc->component.common.fastread) > msg_pdbg2("Fast Read Clock Frequency: %s\n", > - freq_str[desc->component.freq_fastread]); > + pprint_freq(cs, desc->component.common.freq_fastread)); > + if (cs > CHIPSET_6_SERIES_COUGAR_POINT) > + msg_pdbg2("Dual Output Fast Read Support: %sabled\n", > + desc->component.new.dual_output ? "dis" : "en"); > if (desc->component.FLILL == 0) > msg_pdbg2("No forbidden opcodes.\n"); > else { > @@ -273,7 +339,7 @@ static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t of > msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); > > off *= 4; > - switch(conf){ > + switch (conf){ > case 0: > msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); > break; > @@ -723,29 +789,57 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc > #else /* ICH_DESCRIPTORS_FROM_DUMP */ > > /** Returns the integer representation of the component density with index > -idx in bytes or 0 if a correct size can not be determined. */ > -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx) > +\em idx in bytes or -1 if the correct size can not be determined. */ > +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx) > { > + if (idx > 1) { > + msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > + return -1; > + } > + > + if (desc->content.NC == 0 && idx > 0) > + return 0; > + > uint8_t size_enc; > - > - switch(idx) { > - case 0: > - size_enc = desc->component.comp1_density; > + uint8_t size_max; > + > + switch (cs) { > + case CHIPSET_ICH8: > + case CHIPSET_ICH9: > + case CHIPSET_ICH10: > + case CHIPSET_5_SERIES_IBEX_PEAK: > + case CHIPSET_6_SERIES_COUGAR_POINT: > + case CHIPSET_7_SERIES_PANTHER_POINT: > + if (idx == 0) { > + size_enc = desc->component.old.comp1_density; > + } else { > + size_enc = desc->component.old.comp2_density; > + } > + size_max = 5; > break; > - case 1: > - if (desc->content.NC == 0) > - return 0; > - size_enc = desc->component.comp2_density; > + case CHIPSET_8_SERIES_LYNX_POINT: > + case CHIPSET_8_SERIES_LYNX_POINT_LP: > + case CHIPSET_8_SERIES_WELLSBURG: > + if (idx == 0) { > + size_enc = desc->component.new.comp1_density; > + } else { > + size_enc = desc->component.new.comp2_density; > + } > + size_max = 7; > break; > + case CHIPSET_ICH_UNKNOWN: > default: > - msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n"); > - return 0; > + msg_pwarn("Density encoding is unknown on this chipset.\n"); > + return -1; > } > - if (size_enc > 5) { > - msg_perr("Density of ICH SPI component with index %d is invalid. Encoded density is 0x%x.\n", > - idx, size_enc); > - return 0; > + > + if (size_enc > size_max) { > + msg_perr("Density of ICH SPI component with index %d is invalid." > + "Encoded density is 0x%x while maximum allowed is 0x%x.\n", > + idx, size_enc, size_max); > + return -1; > } > + > return (1 << (19 + size_enc)); > } > > diff --git a/ich_descriptors.h b/ich_descriptors.h > index 3a44740..b9213c8 100644 > --- a/ich_descriptors.h > +++ b/ich_descriptors.h > @@ -102,17 +102,44 @@ struct ich_desc_content { > struct ich_desc_component { > union { /* 0x00 */ > uint32_t FLCOMP; /* Flash Components Register */ > + /* FLCOMP encoding on various generations: > + * > + * Chipset/Generation max_speed dual_output density > + * [MHz] bits max. bits > + * ICH8: 33 N/A 5 0:2, 3:5 > + * ICH9: 33 N/A 5 0:2, 3:5 > + * ICH10: 33 N/A 5 0:2, 3:5 > + * Ibex Peak/5: 50 N/A 5 0:2, 3:5 > + * Cougar Point/6: 50 30 5 0:2, 3:5 > + * Patsburg: 50 30 5 0:2, 3:5 > + * Panther Point/7 50 30 5 0:2, 3:5 > + * Lynx Point/8: 50 30 7 0:3, 4:7 > + * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? > + */ > struct { > - uint32_t comp1_density :3, > - comp2_density :3, > - :11, > + uint32_t :17, > freq_read :3, > fastread :1, > freq_fastread :3, > freq_write :3, > freq_read_id :3, > :2; > - }; > + } common; > + struct { > + uint32_t comp1_density :3, > + comp2_density :3, > + :11, > + :13, > + :2; > + } old; > + struct { > + uint32_t comp1_density :4, /* new since Lynx Point/8 */ > + comp2_density :4, > + :9, > + :13, > + dual_output :1, /* new since Cougar Point/6 */ > + :1; > + } new; > }; > union { /* 0x04 */ > uint32_t FLILL; /* Flash Invalid Instructions Register */ > @@ -555,7 +582,7 @@ struct ich_descriptors { > void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); > > void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); > -void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); > void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > > @@ -568,7 +595,7 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struc > #else /* ICH_DESCRIPTORS_FROM_DUMP */ > > int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > -int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx); > +int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); > > #endif /* ICH_DESCRIPTORS_FROM_DUMP */ > #endif /* __ICH_DESCRIPTORS_H__ */ > diff --git a/ichspi.c b/ichspi.c > index 90bb0de..6744bef 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1754,10 +1754,9 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) > > msg_pdbg("\n"); > if (desc_valid) { > - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > - ICH_RET_OK) > - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > - &desc); > + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) > + prettyprint_ich_descriptors(ich_gen, &desc); > + > /* If the descriptor is valid and indicates multiple > * flash devices we need to use hwseq to be able to > * access the second flash device. > @@ -1783,8 +1782,21 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) > "valid. Aborting.\n"); > return ERROR_FATAL; > } > - hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); > - hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); > + > + int tmpi = getFCBA_component_density(ich_generation, &desc, 0); > + if (tmpi < 0) { > + msg_perr("Could not determine density of flash component %d.\n", 0); > + return ERROR_FATAL; > + } > + hwseq_data.size_comp0 = tmpi; > + > + tmpi = getFCBA_component_density(ich_generation, &desc, 1); > + if (tmpi < 0) { > + msg_perr("Could not determine density of flash component %d.\n", 1); > + return ERROR_FATAL; > + } > + hwseq_data.size_comp1 = tmpi; > + > register_opaque_master(&opaque_master_ich_hwseq); > } else { > register_spi_master(&spi_master_ich9); > diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c > index 00ad1f3..4c1f05c 100644 > --- a/util/ich_descriptors_tool/ich_descriptors_tool.c > +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c > @@ -121,6 +121,7 @@ static void usage(char *argv[], char *error) > "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" > "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" > "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" > +"\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" > "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" > "the GbE blob that is required to initialize the GbE are also dumped to files.\n", > argv[0], argv[0]); > @@ -198,6 +199,9 @@ int main(int argc, char *argv[]) > else if ((strcmp(csn, "7") == 0) || > (strcmp(csn, "panther") == 0)) > cs = CHIPSET_7_SERIES_PANTHER_POINT; > + else if ((strcmp(csn, "8") == 0) || > + (strcmp(csn, "lynx") == 0)) > + cs = CHIPSET_8_SERIES_LYNX_POINT; > } > > ret = read_ich_descriptors_from_dump(buf, len, &desc); > -- > Kind regards, Stefan Tauner > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom I tested this branch on CC2: https://github.com/stefanct/flashrom/tree/intel See attached logs. Flashrom views both chips as a single flash space. What is the correct method for only updating a single descriptor area? Note that the descriptor allows r/w everything. I have not tried locking down regions. LGTM Acked-By:Tested-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

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